| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 2788 Value *NegY = Builder.CreateFNegFMF(Y, &I, Y->getName() + ".neg"); in visitFNeg() local
2789 SelectInst *NewSel = SelectInst::Create(Cond, P, NegY); in visitFNeg()
2805 Value *NegY = Builder.CreateFNegFMF(Y, &I, Y->getName() + ".neg"); in visitFNeg() local
2806 SelectInst *NewSel = SelectInst::Create(Cond, NegX, NegY); in visitFNeg()
2822 Value *NegY = Builder.CreateFNeg(Y); in visitFNeg() local
2823 Value *NewCopySign = Builder.CreateCopySign(X, NegY); in visitFNeg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 7349 SDValue NegY = in getNegatedExpression() local
7359 if (NegY != N) in getNegatedExpression()
7360 RemoveDeadNode(NegY); in getNegatedExpression()
7365 if (NegY) { in getNegatedExpression()
7367 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegY, X, Flags); in getNegatedExpression()
7405 SDValue NegY = in getNegatedExpression() local
7415 if (NegY != N) in getNegatedExpression()
7416 RemoveDeadNode(NegY); in getNegatedExpression()
7426 if (NegY) { in getNegatedExpression()
7428 SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, Flags); in getNegatedExpression()
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| H A D | DAGCombiner.cpp | 10139 SDValue NegY = DAG.getNegative(Y, DL, ShiftVT); in visitSHL() local
10141 DAG.getZExtOrTrunc(DAG.getNode(ISD::AND, DL, ShiftVT, Y, NegY), DL, VT); in visitSHL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 1465 Value *NegY = Builder.CreateSub(Zero, Y); in expandDivRem32() local
1466 Value *NegYZ = Builder.CreateMul(NegY, Z); in expandDivRem32()
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| H A D | AMDGPULegalizerInfo.cpp | 4487 auto NegY = B.buildSub(S32, B.buildConstant(S32, 0), Y); in legalizeUnsignedDIV_REM32Impl() local
4488 auto NegYZ = B.buildMul(S32, NegY, Z); in legalizeUnsignedDIV_REM32Impl()
4854 auto NegY = B.buildFNeg(ResTy, Y); in legalizeFastUnsafeFDIV64() local
4861 auto Tmp0 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64()
4864 auto Tmp1 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64()
4868 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X); in legalizeFastUnsafeFDIV64()
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| H A D | AMDGPUISelLowering.cpp | 2260 SDValue NegY = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Y); in LowerUDIVREM() local
2261 SDValue NegYZ = DAG.getNode(ISD::MUL, DL, VT, NegY, Z); in LowerUDIVREM()
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| H A D | SIISelLowering.cpp | 10510 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64() local
10514 SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64()
10517 SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64()
10520 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X); in lowerFastUnsafeFDIV64()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 6063 Register NegY = in matchCombineFSubFMulToFMadOrFMA() local
6066 {NegY, RHS.MI->getOperand(2).getReg(), LHS.Reg}); in matchCombineFSubFMulToFMadOrFMA()
6160 Register NegY = B.buildFNeg(DstTy, FpExtY).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA() local
6164 {NegY, FpExtZ, LHSReg}); in matchCombineFSubFpExtFMulToFMadOrFMA()
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