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Searched refs:NegRHS (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprScalar.cpp4390 bool NegRHS = false; in tryEmitFMulAdd() local
4395 NegRHS = true; in tryEmitFMulAdd()
4413 (RHSBinOp->use_empty() || NegRHS)) { in tryEmitFMulAdd()
4415 if (NegRHS) in tryEmitFMulAdd()
4417 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
4434 (RHSBinOp->use_empty() || NegRHS)) { in tryEmitFMulAdd()
4436 if (NegRHS) in tryEmitFMulAdd()
4438 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1746 APFloat NegRHS = neg(CRHS->getValueAPF()); in combineFMinMaxLegacy() local
1747 if (NegRHS == CFalse->getValueAPF()) { in combineFMinMaxLegacy()
5090 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine() local
5093 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
5228 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHS); in performFNegCombine() local
5231 NegRHS); in performFNegCombine()
H A DSIISelLowering.cpp15305 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFSubCombine() local
15307 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS); in performFSubCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7735 SDValue NegRHS = in getNegatedExpression() local
7741 if (!NegRHS || CostRHS > NegatibleCost::Neutral || in getNegatedExpression()
7745 RemoveDeadNode(NegRHS); in getNegatedExpression()
7750 return DAG.getSelect(DL, VT, Op.getOperand(0), NegLHS, NegRHS); in getNegatedExpression()
H A DDAGCombiner.cpp11839 SDValue NegRHS = TLI.getCheaperOrNeutralNegatedExpression( in combineMinNumMaxNum() local
11841 if (NegRHS) { in combineMinNumMaxNum()
11842 HandleSDNode NegRHSHandle(NegRHS); in combineMinNumMaxNum()
11843 if (NegRHS == False) { in combineMinNumMaxNum()