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Searched refs:NegRHS (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprScalar.cpp4085 bool NegRHS = false; in tryEmitFMulAdd() local
4090 NegRHS = true; in tryEmitFMulAdd()
4108 (RHSBinOp->use_empty() || NegRHS)) { in tryEmitFMulAdd()
4110 if (NegRHS) in tryEmitFMulAdd()
4112 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
4129 (RHSBinOp->use_empty() || NegRHS)) { in tryEmitFMulAdd()
4131 if (NegRHS) in tryEmitFMulAdd()
4133 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1689 APFloat NegRHS = neg(CRHS->getValueAPF()); in combineFMinMaxLegacy() local
1690 if (NegRHS == CFalse->getValueAPF()) { in combineFMinMaxLegacy()
4856 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine() local
4859 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
4994 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHS); in performFNegCombine() local
4997 NegRHS); in performFNegCombine()
H A DSIISelLowering.cpp14370 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFSubCombine() local
14372 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS); in performFSubCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7516 SDValue NegRHS = in getNegatedExpression() local
7522 if (!NegRHS || CostRHS > NegatibleCost::Neutral || in getNegatedExpression()
7526 RemoveDeadNode(NegRHS); in getNegatedExpression()
7531 return DAG.getSelect(DL, VT, Op.getOperand(0), NegLHS, NegRHS); in getNegatedExpression()
H A DDAGCombiner.cpp11306 SDValue NegRHS = TLI.getCheaperOrNeutralNegatedExpression( in combineMinNumMaxNum() local
11308 if (NegRHS) { in combineMinNumMaxNum()
11309 HandleSDNode NegRHSHandle(NegRHS); in combineMinNumMaxNum()
11310 if (NegRHS == False) { in combineMinNumMaxNum()