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Searched refs:Narrow (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX512.td2974 X86VectorVTInfo Narrow,
2976 def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1),
2977 (Narrow.VT Narrow.RC:$src2), cond)),
2980 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2981 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
2982 (X86pcmpm_imm $cc)), Narrow.KRC)>;
2984 def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
2985 (Narrow.KVT (Frag_su:$cc (Narrow.VT Narrow.RC:$src1),
2986 (Narrow.VT Narrow.RC:$src2),
2989 (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC),
[all …]
H A DX86ISelLowering.cpp50925 SDValue Narrow = N.getOperand(0); in PromoteMaskArithmetic() local
50926 EVT NarrowVT = Narrow.getValueType(); in PromoteMaskArithmetic()
50929 SDValue Op = PromoteMaskArithmetic(Narrow, DL, VT, DAG, 0); in PromoteMaskArithmetic()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td1372 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1375 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1378 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1381 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1582 // Scalar Signed Saturating Extract Unsigned Narrow
1586 // Scalar Signed Saturating Extract Narrow
1590 // Scalar Unsigned Saturating Extract Narrow
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2390 bool Narrow = VT.getSizeInBits() == 64; in SelectLoadLane() local
2395 if (Narrow) in SelectLoadLane()
2415 if (Narrow) in SelectLoadLane()
2428 bool Narrow = VT.getSizeInBits() == 64; in SelectPostLoadLane() local
2433 if (Narrow) in SelectPostLoadLane()
2459 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
2467 if (Narrow) in SelectPostLoadLane()
2482 bool Narrow = VT.getSizeInBits() == 64; in SelectStoreLane() local
2487 if (Narrow) in SelectStoreLane()
2510 bool Narrow = VT.getSizeInBits() == 64; in SelectPostStoreLane() local
[all …]
H A DAArch64ISelLowering.cpp4372 SDValue Narrow; in LowerFP_ROUND() local
4379 Narrow = getSVESafeBitCast(I32, SrcVal, DAG); in LowerFP_ROUND()
4383 NaN = DAG.getNode(ISD::OR, DL, I32, Narrow, ImmV(0x400000)); in LowerFP_ROUND()
4388 Narrow = DAG.getNode(AArch64ISD::FCVTX_MERGE_PASSTHRU, DL, MVT::nxv2f32, in LowerFP_ROUND()
4394 NewOps.push_back(Narrow); in LowerFP_ROUND()
4401 SDValue Lsb = DAG.getNode(ISD::SRL, DL, I32, Narrow, ImmV(16)); in LowerFP_ROUND()
4404 Narrow = DAG.getNode(ISD::ADD, DL, I32, Narrow, RoundingBias); in LowerFP_ROUND()
4414 Narrow = DAG.getSelect(DL, I32, IsNaN, NaN, Narrow); in LowerFP_ROUND()
4418 Narrow = DAG.getNode(ISD::SRL, DL, I32, Narrow, ImmV(16)); in LowerFP_ROUND()
4419 return getSVESafeBitCast(VT, Narrow, DAG); in LowerFP_ROUND()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6050 bool Narrow = Ty.getSizeInBits() == 64; in selectVectorLoadLaneIntrinsic() local
6057 if (Narrow) { in selectVectorLoadLaneIntrinsic()
6082 {Narrow ? DstOp(&AArch64::FPR128RegClass) in selectVectorLoadLaneIntrinsic()
6089 if (Narrow && in selectVectorLoadLaneIntrinsic()
6118 bool Narrow = Ty.getSizeInBits() == 64; in selectVectorStoreLaneIntrinsic() local
6124 if (Narrow) in selectVectorStoreLaneIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2568 SDValue Narrow = Op.getOperand(0); in LowerFP_EXTEND() local
2569 EVT NarrowVT = Narrow.getValueType(); in LowerFP_EXTEND()
2575 return DAG.getNode(ISD::BF16_TO_FP, Loc, WideVT, Narrow); in LowerFP_EXTEND()
2583 Op = DAG.getNode(ISD::FP_EXTEND, Loc, F32, Narrow); in LowerFP_EXTEND()
2585 Op = DAG.getNode(ISD::BF16_TO_FP, Loc, F32, Narrow); in LowerFP_EXTEND()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2584 // Narrow 2-register operations.
2593 // Narrow 2-register intrinsics.
3246 // Narrow shift by immediate.
4237 // Neon Shift Narrow operations,
4307 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4309 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
5115 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
5117 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
6012 // VSHRN : Vector Shift Right and Narrow
6039 // VRSHRN : Vector Rounding Shift Right and Narrow
[all …]
H A DARMScheduleSwift.td577 // 4.2.31 Advanced SIMD, Add and Shift with Narrow
/freebsd/contrib/openbsm/
H A DNEWS463 - Narrow set of symbols and defines that are exposed in user space: don't
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td455 // Vector Saturating Narrow
461 // Vector Saturating Extract and Unsigned Narrow
/freebsd/crypto/openssl/doc/designs/quic-design/
H A Dquic-api-ssl-funcs.md199 | **⇒ Narrow Waist Interface** | †4 | | | | …
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp11757 SDValue Narrow = DAG.getFPExtendOrRound(Op, dl, ResultVT); in expandRoundInexactToOdd() local
11758 SDValue NarrowAsWide = DAG.getFPExtendOrRound(Narrow, dl, OperandVT); in expandRoundInexactToOdd()
11763 SDValue NarrowBits = DAG.getNode(ISD::BITCAST, dl, ResultIntVT, Narrow); in expandRoundInexactToOdd()