| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX512.td | 2966 X86VectorVTInfo Narrow,
2968 def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1),
2969 (Narrow.VT Narrow.RC:$src2), cond)),
2972 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2973 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
2974 (X86pcmpm_imm $cc)), Narrow.KRC)>;
2976 def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
2977 (Narrow.KVT (Frag_su:$cc (Narrow.VT Narrow.RC:$src1),
2978 (Narrow.VT Narrow.RC:$src2),
2981 (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC),
[all …]
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| H A D | X86ISelLowering.cpp | 49168 SDValue Narrow = N.getOperand(0); in PromoteMaskArithmetic() local
49169 EVT NarrowVT = Narrow.getValueType(); in PromoteMaskArithmetic()
49172 SDValue Op = PromoteMaskArithmetic(Narrow, DL, VT, DAG, 0); in PromoteMaskArithmetic()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 1352 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1354 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1356 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1358 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1552 // Scalar Signed Saturating Extract Unsigned Narrow
1556 // Scalar Signed Saturating Extract Narrow
1560 // Scalar Unsigned Saturating Extract Narrow
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2290 bool Narrow = VT.getSizeInBits() == 64; in SelectLoadLane() local
2295 if (Narrow) in SelectLoadLane()
2315 if (Narrow) in SelectLoadLane()
2328 bool Narrow = VT.getSizeInBits() == 64; in SelectPostLoadLane() local
2333 if (Narrow) in SelectPostLoadLane()
2359 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
2367 if (Narrow) in SelectPostLoadLane()
2382 bool Narrow = VT.getSizeInBits() == 64; in SelectStoreLane() local
2387 if (Narrow) in SelectStoreLane()
2410 bool Narrow = VT.getSizeInBits() == 64; in SelectPostStoreLane() local
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| H A D | AArch64ISelLowering.cpp | 4303 SDValue Narrow = SrcVal; in LowerFP_ROUND() local
4308 bool NeverSNaN = DAG.isKnownNeverSNaN(Narrow); in LowerFP_ROUND()
4309 Narrow = DAG.getNode(ISD::BITCAST, dl, I32, Narrow); in LowerFP_ROUND()
4312 NaN = DAG.getNode(ISD::OR, dl, I32, Narrow, in LowerFP_ROUND()
4316 Narrow = DAG.getNode(AArch64ISD::FCVTXN, dl, F32, Narrow); in LowerFP_ROUND()
4317 Narrow = DAG.getNode(ISD::BITCAST, dl, I32, Narrow); in LowerFP_ROUND()
4323 SDValue Lsb = DAG.getNode(ISD::SRL, dl, I32, Narrow, in LowerFP_ROUND()
4328 Narrow = DAG.getNode(ISD::ADD, dl, I32, Narrow, RoundingBias); in LowerFP_ROUND()
4337 Narrow = DAG.getSelect(dl, I32, IsNaN, NaN, Narrow); in LowerFP_ROUND()
4341 Narrow = DAG.getNode(ISD::SRL, dl, I32, Narrow, in LowerFP_ROUND()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5890 bool Narrow = Ty.getSizeInBits() == 64; in selectVectorLoadLaneIntrinsic() local
5897 if (Narrow) { in selectVectorLoadLaneIntrinsic()
5922 {Narrow ? DstOp(&AArch64::FPR128RegClass) in selectVectorLoadLaneIntrinsic()
5929 if (Narrow && in selectVectorLoadLaneIntrinsic()
5958 bool Narrow = Ty.getSizeInBits() == 64; in selectVectorStoreLaneIntrinsic() local
5964 if (Narrow) in selectVectorStoreLaneIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2705 SDValue Narrow = Op.getOperand(0); in LowerFP_EXTEND() local
2706 EVT NarrowVT = Narrow.getValueType(); in LowerFP_EXTEND()
2712 return DAG.getNode(ISD::BF16_TO_FP, Loc, WideVT, Narrow); in LowerFP_EXTEND()
2720 Op = DAG.getNode(ISD::FP_EXTEND, Loc, F32, Narrow); in LowerFP_EXTEND()
2722 Op = DAG.getNode(ISD::BF16_TO_FP, Loc, F32, Narrow); in LowerFP_EXTEND()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2584 // Narrow 2-register operations.
2593 // Narrow 2-register intrinsics.
3246 // Narrow shift by immediate.
4237 // Neon Shift Narrow operations,
4307 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4309 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
5115 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
5117 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
6018 // VSHRN : Vector Shift Right and Narrow
6045 // VRSHRN : Vector Rounding Shift Right and Narrow
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| H A D | ARMScheduleSwift.td | 577 // 4.2.31 Advanced SIMD, Add and Shift with Narrow
|
| /freebsd/contrib/openbsm/ |
| H A D | NEWS | 463 - Narrow set of symbols and defines that are exposed in user space: don't
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 455 // Vector Saturating Narrow
461 // Vector Saturating Extract and Unsigned Narrow
|