| /freebsd/contrib/llvm-project/libc/src/__support/FPUtil/x86_64/ |
| H A D | NextAfterLongDouble.h | 51 from_bits = FPBits::min_subnormal(from > to ? Sign::NEG : Sign::POS); in nextafter() 54 if (from_bits == FPBits::max_subnormal(Sign::NEG)) { in nextafter() 57 from_bits = FPBits::min_normal(Sign::NEG); in nextafter() 71 if (from_bits == FPBits::min_normal(Sign::NEG)) { in nextafter() 74 from_bits = FPBits::max_subnormal(Sign::NEG); in nextafter()
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| H A D | NextUpDownLongDouble.h | 26 constexpr Sign sign = IsDown ? Sign::NEG : Sign::POS; in nextupdown()
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| /freebsd/contrib/llvm-project/libc/src/__support/ |
| H A D | sign.h | 30 static const Sign NEG; member 41 LIBC_INLINE_VAR constexpr Sign Sign::NEG = Sign(true);
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| /freebsd/contrib/llvm-project/libc/src/__support/FPUtil/ |
| H A D | ManipulationFunctions.h | 145 return FPBits<T>::inf(Sign::NEG).get_val(); 178 (sign == Sign::NEG && rounding_mode == FE_UPWARD) || 193 (sign == Sign::NEG && rounding_mode == FE_DOWNWARD)) 250 constexpr Sign sign = IsDown ? Sign::NEG : Sign::POS;
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| H A D | dyadic_float.h | 201 return FPBits::inf(Sign::NEG).get_val(); in generic_as() 204 return FPBits::max_normal(Sign::NEG).get_val(); in generic_as() 571 result.sign = (a.sign != b.sign) ? Sign::NEG : Sign::POS; in quick_mul() 594 Sign result_sign = (a.sign != b.sign) ? Sign::NEG : Sign::POS; in rounded_mul()
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| H A D | bfloat16.h | 39 sign = Sign::NEG; in BFloat16()
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| H A D | fpbits_str.h | 63 s += sign_char(x.get_implicit_bit() ? Sign::NEG : Sign::POS); in str()
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| H A D | DivisionAndRemainderOperations.h | 48 (xbits.sign() == ybits.sign() ? Sign::POS : Sign::NEG); in remquo()
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| H A D | NearestIntegerOperations.h | 296 FPBits<T>::create_value(Sign::NEG, range_exp, EXPLICIT_BIT).get_val(); in fromfp()
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| /freebsd/contrib/llvm-project/libc/src/__support/FPUtil/generic/ |
| H A D | add_sub.h | 97 return OutFPBits::zero(Sign::NEG).get_val(); in add_or_sub() 122 return OutFPBits::zero(Sign::NEG).get_val(); in add_or_sub() 136 result_sign = Sign::NEG; in add_or_sub()
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| H A D | mul.h | 44 Sign result_sign = x_bits.sign() == y_bits.sign() ? Sign::POS : Sign::NEG; in mul()
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| H A D | div.h | 43 Sign result_sign = x_bits.sign() == y_bits.sign() ? Sign::POS : Sign::NEG; in div()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600Instructions.td | 57 def NEG : InstFlag <"printNeg">; 105 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 147 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 148 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 187 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 188 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 189 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 1033 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 1034 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 1039 R600_TReg32_Y:$src0_Y, NEG [all...] |
| H A D | GCNDPPCombine.cpp | 140 const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG); in isShrinkable() 289 (0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst() 313 (0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst() 346 (0LL == (Mod2->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
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| H A D | GCNVOPDUtils.cpp | 142 if (Mods && (Mods->getImm() & ~SISrcMods::NEG)) in checkVOPDRegConstraints()
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| H A D | AMDGPUISelDAGToDAG.cpp | 3022 Mods |= SISrcMods::NEG; in SelectVOP3ModsImpl() 3029 Mods |= SISrcMods::NEG; in SelectVOP3ModsImpl() 3151 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI); in SelectVOP3PMods() 3164 Mods ^= SISrcMods::NEG; in SelectVOP3PMods() 3250 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI); in SelectVOP3PMods() 3285 Mods ^= SISrcMods::NEG; in SelectVOP3PModsNeg() 3378 Mods |= SISrcMods::NEG; in selectWMMAModsNegAbs() 3438 Mods |= SISrcMods::NEG; in SelectWMMAModsF16Neg() 3457 Mods |= SISrcMods::NEG; in SelectWMMAModsF16Neg() 3674 if ((ModsTmp & SISrcMods::NEG) != 0) in SelectVOP3PMadMixModsImpl() [all …]
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| H A D | AMDGPUInstructionSelector.cpp | 4177 Mods |= SISrcMods::NEG; in selectVOP3ModsImpl() 4185 Mods |= SISrcMods::NEG; in selectVOP3ModsImpl() 4753 Mods ^= SISrcMods::NEG; in updateMods() 4758 Mods |= SISrcMods::NEG; in updateMods() 4760 Mods ^= SISrcMods::NEG; in updateMods() 4790 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI); in selectVOP3PModsImpl() 4794 Mods ^= SISrcMods::NEG; in selectVOP3PModsImpl() 4916 Mods ^= SISrcMods::NEG; in selectVOP3PModsNeg() 4969 Mods |= SISrcMods::NEG; in selectWMMAModsNegAbs() 5041 Mods |= SISrcMods::NEG; in selectWMMAModsF16Neg() [all …]
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| H A D | SIDefines.h | 268 NEG = 1 << 0, // Floating-point negate modifier enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCScheduleP7.td | 189 NEG, NEG8, NEG8_rec, NEG_rec, NEG8O, NEGO, 243 (instregex "^F(N)?(M)?(R|ADD|SUB|ABS|NEG|NABS|UL)(D|S)?(_rec)?$"), 246 (instregex "^XS(NEG|ABS|NABS|ADD|SUB|MUL)(D|S)P(s)?$"), 260 (instregex "^XV(MAX|MIN|MUL|NEG|ABS|ADD|NABS)(D|S)P$"),
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| H A D | PPCBack2BackFusion.def | 135 NEG, 673 NEG,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.td | 76 def NEG : SDNodeXForm<imm, [{ 342 (SUB_I_LO GPR:$Rs1, (NEG $imm))>; 344 (ADD_I_LO GPR:$Rs1, (NEG $imm))>; 433 def : Pat<(srl GPR:$Rs1, immShift:$imm), (SL_I GPR:$Rs1, (NEG $imm))>; 434 def : Pat<(sra GPR:$Rs1, immShift:$imm), (SA_I GPR:$Rs1, (NEG $imm))>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedKryoDetails.td | 645 (instregex "F(ABS|NEG)(D|S)r")>; 651 (instregex "F(ABS|NEG)v2f32")>; 657 (instregex "F(ABS|NEG)(v2f64|v4f32)")>; 1668 (instregex "NEG(v8i8|v4i16|v2i32|v1i64)")>; 1674 (instregex "NEG(v16i8|v8i16|v4i32|v2i64)")>; 1824 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>; 1830 (instregex "SQ(ABS|NEG)(v8i8|v4i16|v2i32)")>; 1836 (instregex "SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)")>;
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| H A D | AArch64SchedTSV110.td | 484 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "F(ABS|NEG)(D|S)r")>; 557 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(ABS|ADD(P)?|NEG|SUB)v")>; 569 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^((SQ)(ABS|NEG))v")>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrFloat.td | 56 defm NEG : UnaryFP<fneg, "neg ", 0x8c, 0x9a>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 421 (instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)S$")>; 423 (instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)D$")>;
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