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Searched refs:N0Opc (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp4620 unsigned N0Opc = N0->getOpcode(); in SimplifySetCC() local
4621 bool SExt = (N0Opc == ISD::SIGN_EXTEND); in SimplifySetCC()
4624 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && in SimplifySetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19307 unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode(); in performConcatVectorsCombine() local
19323 if (N->getNumOperands() == 2 && N0Opc == ISD::TRUNCATE && in performConcatVectorsCombine()
19390 if (N->getNumOperands() == 2 && N0Opc == ISD::TRUNCATE && in performConcatVectorsCombine()
19420 if (N->getNumOperands() == 2 && N0Opc == N1Opc && VT.is128BitVector() && in performConcatVectorsCombine()
19421 DAG.getTargetLoweringInfo().isBinOp(N0Opc) && N0->hasOneUse() && in performConcatVectorsCombine()
19431 return DAG.getNode(N0Opc, dl, VT, Concat0, Concat1); in performConcatVectorsCombine()
19481 if (N->getNumOperands() == 2 && N0Opc == AArch64ISD::ZIP1 && in performConcatVectorsCombine()