| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1222 SDValue N01 = N0.getOperand(1); in reassociateOpsCommutative() local
1224 if (DAG.isConstantIntBuildVectorOrConstantInt(N01)) { in reassociateOpsCommutative()
1232 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, {N01, N1})) { in reassociateOpsCommutative()
1243 return DAG.getNode(Opc, DL, VT, OpNode, N01, NewFlags); in reassociateOpsCommutative()
1253 if (N1 == N00 || N1 == N01) in reassociateOpsCommutative()
1259 return N01; in reassociateOpsCommutative()
1261 if (N1 == N01) in reassociateOpsCommutative()
1266 if (N1 != N01) { in reassociateOpsCommutative()
1271 if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N01})) in reassociateOpsCommutative()
1272 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N01); in reassociateOpsCommutative()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 4038 SDValue N01 = N0.getOperand(1); in doPeepholeSExtW() local
4042 !isUInt<5>(cast<ConstantSDNode>(N01)->getSExtValue())) in doPeepholeSExtW()
4047 N00, N01); in doPeepholeSExtW()
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| H A D | RISCVISelLowering.cpp | 15552 SDValue N01 = N0.getOperand(1); in combineDeMorganOfBoolean() local
15558 if (isOneConstant(N01)) { in combineDeMorganOfBoolean()
15563 if (!(IsAnd && isAllOnesConstant(N01))) in combineDeMorganOfBoolean()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 49872 SDValue N01 = N0.getOperand(2); in combineShiftLeft() local
49874 if (ISD::isConstantSplatVectorAllZeros(N01.getNode()) && in combineShiftLeft()
49883 return DAG.getNode(X86ISD::VSHLV, DL, VT, N01, N1); in combineShiftLeft()
49964 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic() local
49965 APInt ShlConst = N01->getAsAPIntVal(); in combineShiftRightArithmetic()
49969 if (CVT != N01.getValueType()) in combineShiftRightArithmetic()
50011 SDValue N01 = N0.getOperand(2); in combineShiftRightLogical() local
50013 if (ISD::isConstantSplatVectorAllZeros(N01.getNode()) && in combineShiftRightLogical()
50022 return DAG.getNode(X86ISD::VSRLV, DL, VT, N01, N1); in combineShiftRightLogical()
51010 SDValue N01 = N0.getOperand(1); in convertIntLogicToFPLogic() local
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| H A D | X86ISelDAGToDAG.cpp | 4005 SDValue N01 = N0->getOperand(1); in matchBitExtract() local
4007 if (N1 != N01) in matchBitExtract()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5496 SDValue N01 = skipExtensionForVectorMULL(N0.getOperand(1), DAG); in LowerMUL() local
5504 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)), in LowerMUL()
19940 SDValue N01 = N0->getOperand(IsStrict ? 2 : 1); in performExtractVectorEltCombine() local
19942 ShuffleVectorSDNode *Shuffle = dyn_cast<ShuffleVectorSDNode>(N01); in performExtractVectorEltCombine()
19948 Other = N01; in performExtractVectorEltCombine()
20132 SDValue N01 = N0->getOperand(1); in performConcatVectorsCombine() local
20136 if (!N00.isUndef() && !N01.isUndef() && !N10.isUndef() && !N11.isUndef()) { in performConcatVectorsCombine()
20138 SDValue Concat1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, N01, N11); in performConcatVectorsCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9744 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
9750 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
14220 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
14223 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
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