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Searched refs:N01 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1202 SDValue N01 = N0.getOperand(1); in reassociateOpsCommutative() local
1204 if (DAG.isConstantIntBuildVectorOrConstantInt(peekThroughBitcasts(N01))) { in reassociateOpsCommutative()
1212 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, {N01, N1})) in reassociateOpsCommutative()
1220 return DAG.getNode(Opc, DL, VT, OpNode, N01, NewFlags); in reassociateOpsCommutative()
1230 if (N1 == N00 || N1 == N01) in reassociateOpsCommutative()
1236 return N01; in reassociateOpsCommutative()
1238 if (N1 == N01) in reassociateOpsCommutative()
1243 if (N1 != N01) { in reassociateOpsCommutative()
1248 if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N01})) in reassociateOpsCommutative()
1249 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N01); in reassociateOpsCommutative()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp3491 SDValue N01 = N0.getOperand(1); in doPeepholeSExtW() local
3495 !isUInt<5>(cast<ConstantSDNode>(N01)->getSExtValue())) in doPeepholeSExtW()
3500 N00, N01); in doPeepholeSExtW()
H A DRISCVISelLowering.cpp13562 SDValue N01 = N0.getOperand(1); in combineDeMorganOfBoolean()
13568 if (isOneConstant(N01)) { in combineDeMorganOfBoolean()
13572 // N01 and N11 being 1 was already handled. Handle N11==1 and N01==-1. in combineDeMorganOfBoolean()
13573 if (!(IsAnd && isAllOnesConstant(N01))) in combineDeMorganOfBoolean()
13559 SDValue N01 = N0.getOperand(1); combineDeMorganOfBoolean() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp48117 SDValue N01 = N0.getOperand(2); in combineShiftLeft() local
48119 if (ISD::isConstantSplatVectorAllZeros(N01.getNode()) && in combineShiftLeft()
48128 return DAG.getNode(X86ISD::VSHLV, DL, VT, N01, N1); in combineShiftLeft()
48209 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic() local
48210 APInt ShlConst = N01->getAsAPIntVal(); in combineShiftRightArithmetic()
48214 if (CVT != N01.getValueType()) in combineShiftRightArithmetic()
48256 SDValue N01 = N0.getOperand(2); in combineShiftRightLogical() local
48258 if (ISD::isConstantSplatVectorAllZeros(N01.getNode()) && in combineShiftRightLogical()
48267 return DAG.getNode(X86ISD::VSRLV, DL, VT, N01, N1); in combineShiftRightLogical()
49253 SDValue N01 = N0.getOperand(1); in convertIntLogicToFPLogic() local
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H A DX86ISelDAGToDAG.cpp3939 SDValue N01 = N0->getOperand(1); in matchBitExtract() local
3941 if (N1 != N01) in matchBitExtract()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5345 SDValue N01 = skipExtensionForVectorMULL(N0.getOperand(1), DAG); in LowerMUL() local
5353 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)), in LowerMUL()
19268 SDValue N01 = N0->getOperand(IsStrict ? 2 : 1); in performExtractVectorEltCombine() local
19270 ShuffleVectorSDNode *Shuffle = dyn_cast<ShuffleVectorSDNode>(N01); in performExtractVectorEltCombine()
19276 Other = N01; in performExtractVectorEltCombine()
19427 SDValue N01 = N0->getOperand(1); in performConcatVectorsCombine() local
19431 if (!N00.isUndef() && !N01.isUndef() && !N10.isUndef() && !N11.isUndef()) { in performConcatVectorsCombine()
19433 SDValue Concat1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N01, N11); in performConcatVectorsCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9692 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
9698 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
14143 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
14146 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()