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Searched refs:Mux (Results 1 – 25 of 51) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmdio-mux-multiplexer.txt21 In below example the Mux producer and consumer are separate nodes.
29 mux: mux-controller { // Mux Producer
38 mdio-mux-1 { // Mux consumer
61 mdio-mux-2 { // Mux consumer
/freebsd/sys/contrib/device-tree/Bindings/mux/
H A Dadi,adgs1408.txt1 Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux
29 * Mux state set to idle as is (no idle-state declared)
H A Dmux-controller.txt18 Mux controller consumers should specify a list of mux controllers that they
27 Mux controller properties should be named "mux-controls". The exact meaning of
120 Mux controller nodes
123 Mux controller nodes must specify the number of cells used for the
H A Dadi,adg792a.txt28 * Mux 0 is disconnected when idle, mux 1 idles in the previously
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-mux-gpio.txt1 GPIO-based I2C Bus Mux
12 | | I2C |-|--| Mux |
H A Di2c-mux-gpmux.txt1 General Purpose I2C Bus Mux
12 | | I2C |-|--| Mux |
H A Di2c-mux-pinctrl.txt1 Pinctrl-based I2C Bus Mux
H A Di2c-mux-reg.txt1 Register-based I2C Bus Mux
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dkeystone-reset.txt7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td181 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
189 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
202 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
226 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
228 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
236 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
237 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
239 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
240 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
252 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;
[all …]
H A DSystemZScheduleZ196.td176 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
184 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
194 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
218 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
220 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
228 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
229 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
231 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
232 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
241 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;
[all …]
H A DSystemZScheduleZ13.td197 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
206 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
233 def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
235 (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
237 (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
249 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
251 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
259 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
260 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
[all …]
H A DSystemZScheduleZ16.td199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
208 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
224 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
235 def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
237 (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
239 (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
254 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
256 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
264 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
265 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
[all …]
H A DSystemZScheduleZ15.td199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
208 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
224 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
235 def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
237 (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
239 (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
254 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
256 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
264 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
265 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
[all …]
H A DSystemZScheduleZ14.td198 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
207 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
223 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
234 def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
236 (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
238 (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
250 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
252 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
260 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
261 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dimx-audmux.txt1 Freescale Digital Audio Mux (AUDMUX) device
/freebsd/sys/contrib/device-tree/Bindings/iio/multiplexer/
H A Dio-channel-mux.txt13 - mux-controls : Mux controller node to use for operating the mux
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-librem5-devkit.dts152 sound-name-prefix = "Mic Mux";
168 "MIC_IN", "Mic Mux OUT",
169 "Mic Mux IN1", "Headset Microphone",
170 "Mic Mux IN2", "Builtin Microphone",
171 "Mic Mux OUT", "Mic Bias",
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Doxnas,pinctrl.txt20 - function: Mux function for the specified pins.
H A Dmicrochip,pic32-pinctrl.txt21 - function: Mux function for the specified pins.
H A Dnvidia,tegra210-pinmux.txt81 Mux groups:
149 <0x0 0x70003000 0x0 0x1000>; /* Mux registers */
H A Drenesas,pfc-pinctrl.txt1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config)
3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
H A Dnvidia,tegra194-pinmux.txt62 Mux groups:
H A Dnvidia,tegra30-pinmux.txt111 0x70003000 0x3e0 >; /* Mux registers */
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-href-family-pinctrl.dtsi75 /* Mux in VSI0 and all the data lines */

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