| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineInternal.h | 221 bool fmulByZeroIsZero(Value *MulVal, FastMathFlags FMF,
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| H A D | InstCombineCompares.cpp | 6145 static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal, in processUMulZExtIdiom() argument
6150 if (!isa<IntegerType>(MulVal->getType())) in processUMulZExtIdiom()
6153 auto *MulInstr = dyn_cast<Instruction>(MulVal); in processUMulZExtIdiom()
6181 if (MulVal->hasNUsesOrMore(2)) in processUMulZExtIdiom()
6182 for (User *U : MulVal->users()) { in processUMulZExtIdiom()
6254 if (MulVal->hasNUsesOrMore(2)) { in processUMulZExtIdiom()
6256 for (User *U : make_early_inc_range(MulVal->users())) { in processUMulZExtIdiom()
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| H A D | InstCombineSelect.cpp | 3532 bool InstCombinerImpl::fmulByZeroIsZero(Value *MulVal, FastMathFlags FMF, in fmulByZeroIsZero() argument
3534 KnownFPClass Known = computeKnownFPClass(MulVal, FMF, fcNegative, CtxI); in fmulByZeroIsZero()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2584 SDValue MulVal = N.getOperand(0); in matchAddressRecursively() local
2590 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && in matchAddressRecursively()
2591 isa<ConstantSDNode>(MulVal.getOperand(1))) { in matchAddressRecursively()
2592 Reg = MulVal.getOperand(0); in matchAddressRecursively()
2593 auto *AddVal = cast<ConstantSDNode>(MulVal.getOperand(1)); in matchAddressRecursively()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4301 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); in performMulCombine() local
4302 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
4306 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper); in performMulCombine() local
4307 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0); in performMulCombine()
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| H A D | AMDGPULegalizerInfo.cpp | 2825 auto MulVal = B.buildFMul(Ty, SrcReg, OneOver2Pi, Flags); in legalizeSinCos() local
2827 .addUse(MulVal.getReg(0)) in legalizeSinCos()
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| H A D | SIISelLowering.cpp | 11161 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi, Flags); in LowerTrig() local
11162 TrigVal = DAG.getNode(AMDGPUISD::FRACT, DL, VT, MulVal, Flags); in LowerTrig()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 5711 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt; in TryMULWIDECombine() local
5712 RHS = DCI.DAG.getConstant(MulVal, DL, MulType); in TryMULWIDECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14082 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); in performMULCombine() local
14083 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMULCombine()
14087 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); in performMULCombine() local
14088 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMULCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18278 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); in performMulCombine() local
18279 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMulCombine()
18283 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); in performMulCombine() local
18284 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMulCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4503 APInt MulVal; in visitMUL() local
4505 ISD::isConstantSplatVector(N1.getNode(), MulVal)) { in visitMUL()
4507 APInt NewStep = C0 * MulVal; in visitMUL()
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