Searched refs:Mul2 (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 2113 WeightedLeaf Mul1, Mul2; in balanceSubTree() local
2166 Mul2 = WeightedLeaf(Child, Weight, InsertionOrder++); in balanceSubTree()
2226 willShiftRightEliminate(Mul2.Value, MaxPowerOf2))) { in balanceSubTree()
2228 int Weight = Mul1.Weight + Mul2.Weight; in balanceSubTree()
2229 int Height = std::max(NodeHeights[Mul1.Value], NodeHeights[Mul2.Value]) + 1; in balanceSubTree()
2231 SDValue Mul2Factored = factorOutPowerOf2(Mul2.Value, MaxPowerOf2); in balanceSubTree()
2244 if (Mul2.Value.getNode()) in balanceSubTree()
2245 Leaves.push(Mul2); in balanceSubTree()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1438 let ParserMatchClass = ZPRVectorListMul<0, 2, "Mul2">;
1442 let ParserMatchClass = ZPRVectorListMul<8, 2, "Mul2">;
1446 let ParserMatchClass = ZPRVectorListMul<16, 2, "Mul2">;
1450 let ParserMatchClass = ZPRVectorListMul<32, 2, "Mul2">;
1454 let ParserMatchClass = ZPRVectorListMul<64, 2, "Mul2">;
1458 let ParserMatchClass = ZPRVectorListMul<128, 2, "Mul2">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2644 MachineOperand &Mul2 = Prev.getOperand(2); in combineFPFusedMultiply() local
2655 bool Mul2IsKill = Mul2.isKill(); in combineFPFusedMultiply()
2662 MRI.clearKillFlags(Mul2.getReg()); in combineFPFusedMultiply()
2667 .addReg(Mul2.getReg(), getKillRegState(Mul2IsKill)) in combineFPFusedMultiply()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2135 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64() local
2137 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 4599 auto Mul2 = B.buildFMul( in emitReciprocalU64() local
4601 auto Trunc = B.buildIntrinsicTrunc(S32, Mul2); in emitReciprocalU64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29825 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, in LowerMULH() local
29834 SDValue Res = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, ShufMask); in LowerMULH()
49406 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
49410 DAG.getConstant(Mul2, DL, VT)); in combineMulSpecial()
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