/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMParallelDSP.cpp | 144 void AddMulPair(MulCandidate *Mul0, MulCandidate *Mul1, in AddMulPair() argument 148 << *Mul1->Root << "\n"); in AddMulPair() 150 Mul1->Paired = true; in AddMulPair() 152 Mul1->Exchange = true; in AddMulPair() 153 MulPairs.push_back(std::make_pair(Mul0, Mul1)); in AddMulPair() 610 const Instruction *Mul1 = PMul1->Root; in CreateParallelPairs() local 611 if (Mul0 == Mul1) in CreateParallelPairs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 2102 WeightedLeaf Mul1, Mul2; in balanceSubTree() local 2151 if (!Mul1.Value.getNode()) { in balanceSubTree() 2152 Mul1 = WeightedLeaf(Child, Weight, InsertionOrder++); in balanceSubTree() 2214 if (CanFactorize && (willShiftRightEliminate(Mul1.Value, MaxPowerOf2) || in balanceSubTree() 2217 int Weight = Mul1.Weight + Mul2.Weight; in balanceSubTree() 2218 int Height = std::max(NodeHeights[Mul1.Value], NodeHeights[Mul2.Value]) + 1; in balanceSubTree() 2219 SDValue Mul1Factored = factorOutPowerOf2(Mul1.Value, MaxPowerOf2); in balanceSubTree() 2221 SDValue Sum = CurDAG->getNode(ISD::ADD, SDLoc(N), Mul1.Value.getValueType(), in balanceSubTree() 2224 Mul1.Value.getValueType()); in balanceSubTree() 2225 SDValue New = CurDAG->getNode(ISD::SHL, SDLoc(N), Mul1.Value.getValueType(), in balanceSubTree() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 570 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, in isADDADDMUL() argument 595 Mul1 = OtherOp.getOperand(1); in isADDADDMUL() 605 Mul1 = AddOp.getOperand(0).getOperand(1); in isADDADDMUL() 615 Mul1 = AddOp.getOperand(1).getOperand(1); in isADDADDMUL() 1646 SDValue Mul0, Mul1, Addend0, Addend1; in PerformDAGCombine() local 1648 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { in PerformDAGCombine() 1651 Mul1, Addend0, Addend1); in PerformDAGCombine() 1661 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && in PerformDAGCombine() 1663 DAG.MaskedValueIsZero(Mul1, HighMask) && in PerformDAGCombine() 1669 Mul1, DAG.getConstant(0, dl, MVT::i32)); in PerformDAGCombine()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 2224 MachineOperand &Mul1 = Prev.getOperand(1); in combineFPFusedMultiply() local 2235 bool Mul1IsKill = Mul1.isKill(); in combineFPFusedMultiply() 2242 MRI.clearKillFlags(Mul1.getReg()); in combineFPFusedMultiply() 2247 .addReg(Mul1.getReg(), getKillRegState(Mul1IsKill)) in combineFPFusedMultiply()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 2076 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64() local 2078 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64() 2083 Mul1); in LowerUDIVREM64() 2936 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, X, K1, Flags); in lowerFEXP10Unsafe() local 2937 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe() 2962 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K1, Flags); in lowerFEXP10Unsafe() local 2963 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
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H A D | AMDGPULegalizerInfo.cpp | 4537 auto Mul1 = B.buildFMul( in emitReciprocalU64() local 4542 S32, Mul1, B.buildFConstant(S32, llvm::bit_cast<float>(0x2f800000))); in emitReciprocalU64() 4548 Mul1); in emitReciprocalU64() 5167 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags); in legalizeFDIVFastIntrin() local 5169 B.buildFMul(Res, Sel, Mul1, Flags); in legalizeFDIVFastIntrin()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 28756 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, in LowerMULH() local 28770 SDValue Res = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, ShufMask); in LowerMULH() 47635 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument 47637 DAG.getConstant(Mul1, DL, VT)); in combineMulSpecial()
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