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Searched refs:MidVT (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp5076 MVT MidVT = OldEltsPerNewElt == 1 in getPromotedVectorElementType() local
5079 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType()
5080 return MidVT; in getPromotedVectorElementType()
5609 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
5613 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op)); in PromoteNode()
5617 DAG.getNode(MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS, in PromoteNode()
5642 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
5643 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
5663 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps); in PromoteNode()
5688 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
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H A DLegalizeFloatTypes.cpp612 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local
617 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp4206 EVT MidVT = VT.isVector() ? in performTruncateCombine() local
4210 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout()); in performTruncateCombine()
4211 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
4220 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19335 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local
19336 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine()
19341 MidVT, dl, in performConcatVectorsCombine()
19342 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
19343 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp51081 EVT MidVT = VT.changeVectorElementType(MVT::i16); in combineTruncateWithSat() local
51082 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat()