Searched refs:MidReg4 (Results 1 – 1 of 1) sorted by relevance
8251 Register MidReg4 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitCountOp() local8262 BuildMI(MBB, MII, DL, get(AMDGPU::V_MIN_U32_e64), MidReg4) in splitScalar64BitCountOp()8266 MRI.replaceRegWith(Dest.getReg(), MidReg4); in splitScalar64BitCountOp()8268 addUsersToMoveToVALUWorklist(MidReg4, MRI, Worklist); in splitScalar64BitCountOp()