Searched refs:MidReg3 (Results 1 – 1 of 1) sorted by relevance
8250 Register MidReg3 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitCountOp() local8257 BuildMI(MBB, MII, DL, get(OpcodeAdd), MidReg3) in splitScalar64BitCountOp()8263 .addReg(MidReg3) in splitScalar64BitCountOp()