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Searched refs:MidReg (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp243 Register MidReg = I1->getOperand(0).getReg(); in matchExtAddvToUdotAddv() local
245 LLT MidTy = MRI.getType(MidReg); in matchExtAddvToUdotAddv()
254 if (!MRI.hasOneNonDBGUse(MidReg)) in matchExtAddvToUdotAddv()
H A DAArch64LegalizerInfo.cpp1760 Register MidReg = in legalizeIntrinsic() local
1765 {MidReg, ZeroReg}) in legalizeIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp3519 Register MidReg; in applyUseVectorTruncate() local
3529 MidReg = MatchInfo; in applyUseVectorTruncate()
3537 MidReg = Builder.buildConcatVectors(MidTy, ConcatRegs).getReg(0); in applyUseVectorTruncate()
3540 Builder.buildTrunc(DstReg, MidReg); in applyUseVectorTruncate()
H A DLegalizerHelper.cpp3063 Register MidReg = in widenScalar() local
3065 NewDst = MIRBuilder.buildSMax(WideTy, MidReg, MinVal).getReg(0); in widenScalar()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp8624 Register MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
8635 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0); in splitScalar64BitBCNT()
8637 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg); in splitScalar64BitBCNT()