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Searched refs:MemI (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopDataPrefetch.cpp241 Instruction *MemI = nullptr; member
255 MemI = I; in addInstruction()
328 Instruction *MemI; in runOnLoop() local
331 MemI = LMemI; in runOnLoop()
335 MemI = SMemI; in runOnLoop()
362 Pref.addInstruction(MemI, DT, PD); in runOnLoop()
369 Prefetches.push_back(Prefetch(LSCEVAddRec, MemI)); in runOnLoop()
412 << *P.MemI->getOperand(isa<LoadInst>(P.MemI) ? 0 : 1) in runOnLoop()
415 return OptimizationRemark(DEBUG_TYPE, "Prefetched", P.MemI) in runOnLoop()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLoopInstrFormPrep.cpp252 bool alreadyPrepared(Loop *L, Instruction *MemI,
257 Value *getNodeForInc(Loop *L, Instruction *MemI,
282 void addOneCandidate(Instruction *MemI, const SCEV *LSCEV,
365 static Value *getPointerOperandAndType(Value *MemI, in getPointerOperandAndType() argument
371 if (LoadInst *LMemI = dyn_cast<LoadInst>(MemI)) { in getPointerOperandAndType()
374 } else if (StoreInst *SMemI = dyn_cast<StoreInst>(MemI)) { in getPointerOperandAndType()
377 } else if (IntrinsicInst *IMemI = dyn_cast<IntrinsicInst>(MemI)) { in getPointerOperandAndType()
378 PointerElementType = Type::getInt8Ty(MemI->getContext()); in getPointerOperandAndType()
827 Instruction *MemI, const SCEV *LSCEV, SmallVector<Bucket, 16> &Buckets, in addOneCandidate() argument
829 assert((MemI && getPointerOperandAndType(MemI)) && in addOneCandidate()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/
H A DSeedCollector.h151 explicit MemSeedBundle(LoadOrStoreT *MemI) : SeedBundle(MemI) { in MemSeedBundle() argument
155 assert(isa<LoadOrStoreT>(MemI) && "Expected Load or Store!"); in MemSeedBundle()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoadStoreWidening.cpp375 for (auto MemI : Other) in createGroup() local
376 if (!canSwapInstructions(MI, MemI)) in createGroup()
382 for (auto MemI : Other) { in createGroup() local
383 if (std::distance(Group.back()->getIterator(), MemI->getIterator()) <= in createGroup()
387 if (!canSwapInstructions(MemI, GI)) in createGroup()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2999 AArch64InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI, in getAddrModeFromMemoryOp() argument
3004 if (!getMemOperandWithOffset(MemI, Base, Offset, OffsetIsScalable, TRI)) in getAddrModeFromMemoryOp()
3017 bool AArch64InstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, in canFoldIntoAddrMode() argument
3024 switch (MemI.getOpcode()) { in canFoldIntoAddrMode()
3124 const MachineOperand &BaseRegOp = MemI.getOperand(0); in canFoldIntoAddrMode()
3129 if (MemI.getOperand(2).isReg()) { in canFoldIntoAddrMode()
3132 if (MemI.getOperand(3).getImm()) in canFoldIntoAddrMode()
3136 if (MemI.getOperand(4).getImm() == 0) in canFoldIntoAddrMode()
3142 if (MemI.getOperand(1).getReg() == Reg && OffsetScale != 1) in canFoldIntoAddrMode()
3158 AM.BaseReg = MemI.getOperand(1).getReg(); in canFoldIntoAddrMode()
[all …]
H A DAArch64InstrInfo.h292 getAddrModeFromMemoryOp(const MachineInstr &MemI,
295 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
299 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h166 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
170 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
H A DRISCVInstrInfo.cpp3045 bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, in canFoldIntoAddrMode() argument
3048 switch (MemI.getOpcode()) { in canFoldIntoAddrMode()
3077 if (MemI.getOperand(0).getReg() == Reg) in canFoldIntoAddrMode()
3084 int64_t OldOffset = MemI.getOperand(2).getImm(); in canFoldIntoAddrMode()
3101 MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI, in emitLdStWithAddr() argument
3104 const DebugLoc &DL = MemI.getDebugLoc(); in emitLdStWithAddr()
3105 MachineBasicBlock &MBB = *MemI.getParent(); in emitLdStWithAddr()
3110 return BuildMI(MBB, MemI, DL, get(MemI.getOpcode())) in emitLdStWithAddr()
3111 .addReg(MemI.getOperand(0).getReg(), in emitLdStWithAddr()
3112 MemI.mayLoad() ? RegState::Define : 0) in emitLdStWithAddr()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineLoadStoreAlloca.cpp899 GetElementPtrInst *GEPI, Instruction *MemI, in canReplaceGEPIdxWithZero() argument
947 KnownBits Known = IC.computeKnownBits(GEPI->getOperand(i), MemI); in canReplaceGEPIdxWithZero()
974 Instruction &MemI) { in replaceGEPIdxWithZero() argument
977 if (canReplaceGEPIdxWithZero(IC, GEPI, &MemI, Idx)) { in replaceGEPIdxWithZero()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1473 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction() local
1475 MemI < MVT::VALUETYPE_SIZE && "Table isn't big enough!"); in getLoadExtAction()
1477 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf); in getLoadExtAction()
1497 unsigned MemI = (unsigned)MemVT.getSimpleVT().SimpleTy; in getAtomicLoadExtAction() local
1499 MemI < MVT::VALUETYPE_SIZE && "Table isn't big enough!"); in getAtomicLoadExtAction()
1502 (LegalizeAction)((AtomicLoadExtActions[ValI][MemI] >> Shift) & 0xf); in getAtomicLoadExtAction()
1520 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getTruncStoreAction() local
1521 assert(ValI < MVT::VALUETYPE_SIZE && MemI < MVT::VALUETYPE_SIZE && in getTruncStoreAction()
1523 return TruncStoreActions[ValI][MemI]; in getTruncStoreAction()
H A DTargetInstrInfo.h1570 getAddrModeFromMemoryOp(const MachineInstr &MemI, in getAddrModeFromMemoryOp() argument
1581 virtual bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, in canFoldIntoAddrMode() argument
1590 virtual MachineInstr *emitLdStWithAddr(MachineInstr &MemI, in emitLdStWithAddr() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h435 getAddrModeFromMemoryOp(const MachineInstr &MemI,
H A DX86InstrInfo.cpp4554 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI, in getAddrModeFromMemoryOp() argument
4556 const MCInstrDesc &Desc = MemI.getDesc(); in getAddrModeFromMemoryOp()
4563 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp()
4567 const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp); in getAddrModeFromMemoryOp()
4574 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp()
4575 AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm(); in getAddrModeFromMemoryOp()