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Searched refs:MatchInfo (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h191 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
192 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
195 bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo);
199 bool matchCombineExtractedVectorLoad(MachineInstr &MI, BuildFnTy &MatchInfo);
201 bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
202 void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
208 bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
209 void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
296 bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
297 void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombinerHelper.cpp193 MachineInstr *&MatchInfo) { in matchFoldableFneg() argument
195 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
205 if (fnegFoldsIntoMI(*MatchInfo) && in matchFoldableFneg()
207 !allUsesHaveSourceMods(*MatchInfo, MRI))) in matchFoldableFneg()
211 switch (MatchInfo->getOpcode()) { in matchFoldableFneg()
221 return !isConstantCostlierToNegate(*MatchInfo, in matchFoldableFneg()
222 MatchInfo->getOperand(2).getReg(), MRI); in matchFoldableFneg()
227 return mayIgnoreSignedZero(*MatchInfo); in matchFoldableFneg()
242 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID(); in matchFoldableFneg()
251 return mayIgnoreSignedZero(*MatchInfo); in matchFoldableFneg()
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H A DAMDGPUPreLegalizerCombiner.cpp72 ClampI64ToI16MatchInfo &MatchInfo) const;
75 const ClampI64ToI16MatchInfo &MatchInfo) const;
118 ClampI64ToI16MatchInfo &MatchInfo) const { in matchClampI64ToI16()
132 auto IsApplicableForCombine = [&MatchInfo]() -> bool { in matchClampI64ToI16()
133 const auto Cmp1 = MatchInfo.Cmp1; in matchClampI64ToI16()
134 const auto Cmp2 = MatchInfo.Cmp2; in matchClampI64ToI16()
152 m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16()
154 m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
160 m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16()
162 m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
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H A DAMDGPUPostLegalizerCombiner.cpp83 std::function<void(MachineIRBuilder &)> &MatchInfo) const;
96 CvtF32UByteMatchInfo &MatchInfo) const;
98 const CvtF32UByteMatchInfo &MatchInfo) const;
105 MachineInstr &MI, std::pair<MachineInstr *, unsigned> &MatchInfo) const;
107 MachineInstr &MI, std::pair<MachineInstr *, unsigned> &MatchInfo) const;
252 std::function<void(MachineIRBuilder &)> &MatchInfo) const { in matchRcpSqrtToRsq()
277 MatchInfo = [SqrtSrcMI, &MI](MachineIRBuilder &B) { in matchRcpSqrtToRsq()
287 MatchInfo = [RcpSrcMI, &MI](MachineIRBuilder &B) { in matchRcpSqrtToRsq()
318 MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) const { in matchCvtF32UByteN()
336 MatchInfo.CvtVal = Src0; in matchCvtF32UByteN()
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H A DAMDGPURegBankCombiner.cpp85 bool matchIntMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo) const;
86 bool matchFPMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo) const;
89 void applyMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo) const;
193 MachineInstr &MI, Med3MatchInfo &MatchInfo) const { in matchIntMinMaxToMed3()
215 MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg}; in matchIntMinMaxToMed3()
238 MachineInstr &MI, Med3MatchInfo &MatchInfo) const { in matchFPMinMaxToMed3()
268 MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg}; in matchFPMinMaxToMed3()
359 Med3MatchInfo &MatchInfo) const { in applyMed3()
360 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)}, in applyMed3()
361 {getAsVgpr(MatchInfo.Val0), getAsVgpr(MatchInfo.Val1), in applyMed3()
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H A DAMDGPUCombinerHelper.h27 bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
28 void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperVectorOps.cpp34 BuildFnTy &MatchInfo) { in matchExtractVectorElement() argument
84 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchExtractVectorElement()
92 const MachineOperand &MO, BuildFnTy &MatchInfo) { in matchExtractVectorElementWithDifferentIndices() argument
139 MatchInfo = [=](MachineIRBuilder &B) { in matchExtractVectorElementWithDifferentIndices()
149 const MachineOperand &MO, BuildFnTy &MatchInfo) { in matchExtractVectorElementWithBuildVector() argument
202 MatchInfo = [=](MachineIRBuilder &B) { in matchExtractVectorElementWithBuildVector()
210 const MachineOperand &MO, BuildFnTy &MatchInfo) { in matchExtractVectorElementWithBuildVectorTrunc() argument
269 MatchInfo = [=](MachineIRBuilder &B) { in matchExtractVectorElementWithBuildVectorTrunc()
277 const MachineOperand &MO, BuildFnTy &MatchInfo) { in matchExtractVectorElementWithShuffleVector() argument
345 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchExtractVectorElementWithShuffleVector()
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H A DCombinerHelper.cpp227 MachineInstr &MI, BuildFnTy &MatchInfo) { in matchFreezeOfSingleMaybePoisonOperand() argument
270 MatchInfo = [=](MachineIRBuilder &B) { in matchFreezeOfSingleMaybePoisonOperand()
282 MatchInfo = [=](MachineIRBuilder &B) mutable { in matchFreezeOfSingleMaybePoisonOperand()
887 BuildFnTy &MatchInfo) { in matchCombineLoadWithAndMask() argument
957 MatchInfo = [=](MachineIRBuilder &B) { in matchCombineLoadWithAndMask()
1030 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in matchSextInRegOfLoad() argument
1077 MatchInfo = std::make_tuple(LoadDef->getDstReg(), NewSizeBits); in matchSextInRegOfLoad()
1082 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in applySextInRegOfLoad() argument
1086 std::tie(LoadReg, ScalarSizeBits) = MatchInfo; in applySextInRegOfLoad()
1320 BuildFnTy &MatchInfo) { in matchCombineExtractedVectorLoad() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp158 ShuffleVectorPseudo &MatchInfo) { in matchREV() argument
183 MatchInfo = ShuffleVectorPseudo(Opcode, Dst, {Src}); in matchREV()
194 ShuffleVectorPseudo &MatchInfo) { in matchTRN() argument
205 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchTRN()
215 ShuffleVectorPseudo &MatchInfo) { in matchUZP() argument
226 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchUZP()
231 ShuffleVectorPseudo &MatchInfo) { in matchZip() argument
242 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchZip()
249 ShuffleVectorPseudo &MatchInfo) { in matchDupFromInsertVectorElt() argument
281 MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), in matchDupFromInsertVectorElt()
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H A DAArch64PreLegalizerCombiner.cpp77 GISelKnownBits *KB, Register &MatchInfo) { in matchICmpRedundantTrunc() argument
101 MatchInfo = WideReg; in matchICmpRedundantTrunc()
127 std::pair<uint64_t, uint64_t> &MatchInfo) { in matchFoldGlobalOffset() argument
189 MatchInfo = std::make_pair(NewOffset, MinOffset); in matchFoldGlobalOffset()
195 std::pair<uint64_t, uint64_t> &MatchInfo) { in applyFoldGlobalOffset() argument
217 std::tie(Offset, MinOffset) = MatchInfo; in applyFoldGlobalOffset()
237 std::tuple<Register, Register, bool> &MatchInfo) { in matchExtAddvToUdotAddv() argument
269 std::get<0>(MatchInfo) = ExtMI1->getOperand(1).getReg(); in matchExtAddvToUdotAddv()
270 std::get<1>(MatchInfo) = ExtMI2->getOperand(1).getReg(); in matchExtAddvToUdotAddv()
273 std::get<0>(MatchInfo) = I1->getOperand(1).getReg(); in matchExtAddvToUdotAddv()
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H A DAArch64PostLegalizerCombiner.cpp68 std::tuple<unsigned, LLT, Register> &MatchInfo) { in matchExtractVecEltPairwiseAdd() argument
101 std::get<0>(MatchInfo) = TargetOpcode::G_FADD; in matchExtractVecEltPairwiseAdd()
102 std::get<1>(MatchInfo) = DstTy; in matchExtractVecEltPairwiseAdd()
103 std::get<2>(MatchInfo) = Other->getOperand(0).getReg(); in matchExtractVecEltPairwiseAdd()
111 std::tuple<unsigned, LLT, Register> &MatchInfo) { in applyExtractVecEltPairwiseAdd() argument
112 unsigned Opc = std::get<0>(MatchInfo); in applyExtractVecEltPairwiseAdd()
115 LLT Ty = std::get<1>(MatchInfo); in applyExtractVecEltPairwiseAdd()
116 Register Src = std::get<2>(MatchInfo); in applyExtractVecEltPairwiseAdd()
346 std::tuple<Register, Register, Register> &MatchInfo) { in matchOrToBSP() argument
372 MatchInfo = {AO1, AO2, BVO1}; in matchOrToBSP()
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/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/LogicalView/Core/
H A DLVOptions.cpp506 bool LVPatterns::matchPattern(StringRef Input, const LVMatchInfo &MatchInfo) { in matchPattern() argument
512 for (const LVMatch &Match : MatchInfo) { in matchPattern()
/freebsd/contrib/llvm-project/llvm/lib/FileCheck/
H A DFileCheck.cpp1144 SmallVector<StringRef, 4> MatchInfo; in match() local
1148 if (!Regex(RegExToMatch, Flags).match(Buffer, &MatchInfo)) in match()
1152 assert(!MatchInfo.empty() && "Didn't get any match"); in match()
1153 StringRef FullMatch = MatchInfo[0]; in match()
1157 assert(VariableDef.second < MatchInfo.size() && "Internal paren error"); in match()
1159 MatchInfo[VariableDef.second]; in match()
1175 assert(CaptureParenGroup < MatchInfo.size() && "Internal paren error"); in match()
1179 StringRef MatchedValue = MatchInfo[CaptureParenGroup]; in match()
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/LogicalView/Core/
H A DLVOptions.h597 bool matchPattern(StringRef Input, const LVMatchInfo &MatchInfo);
/freebsd/contrib/sqlite3/
H A Dsqlite3.c202399 typedef struct MatchInfo MatchInfo;
202400 struct MatchInfo {
203176 MatchInfo *p /* Matchinfo context */
203214 MatchInfo *p
203261 MatchInfo *p = (MatchInfo *)pCtx;
203278 MatchInfo *p = (MatchInfo *)pCtx;
203316 static size_t fts3MatchinfoSize(MatchInfo *pInfo, char cArg){
203452 static int fts3MatchinfoLcs(Fts3Cursor *pCsr, MatchInfo *pInfo){
203543 MatchInfo *pInfo, /* Matchinfo context object */
203667 MatchInfo sInfo;
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