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Searched refs:MaskReg (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp303 Register MaskReg, Register ScratchReg) { in doMaskedAtomicBinOpExpansion()
305 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in doMaskedAtomicBinOpExpansion()
306 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in doMaskedAtomicBinOpExpansion() local
316 .addReg(MaskReg); in doMaskedAtomicBinOpExpansion()
334 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion()
376 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in expandAtomicBinOp()
475 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp()
491 .addReg(MaskReg); in expandAtomicMinMaxOp()
278 insertMaskedMerge(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
446 Register MaskReg = MI.getOperand(5).getReg(); expandAtomicMinMaxOp() local
544 tryToFoldBNEOnCmpXchgResult(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,Register CmpValReg,Register MaskReg,MachineBasicBlock * & LoopHeadBNETarget) tryToFoldBNEOnCmpXchgResult() argument
611 Register MaskReg = IsMasked ? MI.getOperand(5).getReg() : Register(); expandAtomicCmpXchg() local
659 Register MaskReg = MI.getOperand(5).getReg(); expandAtomicCmpXchg() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp221 Register MaskReg, Register ScratchReg) { in doAtomicBinOpExpansion()
223 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique");
224 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
232 .addReg(MaskReg); in insertMaskedMerge()
247 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion()
288 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
386 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp()
398 .addReg(MaskReg); in expandAtomicMinMaxOp()
227 insertMaskedMerge(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
253 Register MaskReg = MI.getOperand(4).getReg(); doMaskedAtomicBinOpExpansion() local
401 Register MaskReg = MI.getOperand(5).getReg(); expandAtomicMinMaxOp() local
562 Register MaskReg = MI.getOperand(5).getReg(); expandAtomicCmpXchg() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp232 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
233 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
234 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
H A DLegalizerHelper.cpp8470 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
8485 Register MaskElt = MaskReg; in lowerSelect()
8499 MaskReg = ShufSplat.getReg(0); in lowerSelect()
8501 MaskReg = MaskElt; in lowerSelect()
8513 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
8514 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2899 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
2901 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
2907 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2914 APInt MaskOnes = KB->getKnownOnes(MaskReg).zext(64); in selectG_PTRMASK()
2925 .addReg(MaskReg) in selectG_PTRMASK()
2942 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
2951 .addReg(MaskReg); in selectG_PTRMASK()
2979 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2993 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
H A DAMDGPURegisterBankInfo.cpp4810 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
4811 unsigned MaskSize = MRI.getType(MaskReg).getSizeInBits(); in getInstrMapping()
4812 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4819 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
4820 unsigned MaskSize = MRI.getType(MaskReg).getSizeInBits(); in getInstrMapping()
4821 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4837 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
4838 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h575 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
H A DAArch64InstrInfo.cpp1481 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr() argument
1483 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12272 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
12348 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
12362 .addReg(MaskReg); in EmitPartwordAtomicBinary()
12363 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
12371 .addReg(MaskReg); in EmitPartwordAtomicBinary()
13287 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
13372 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
13377 .addReg(MaskReg); in EmitInstrWithCustomInserter()
13380 .addReg(MaskReg); in EmitInstrWithCustomInserter()
13388 .addReg(MaskReg); in EmitInstrWithCustomInserter()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp3130 Register MaskReg = I.getOperand(2).getReg(); in select() local
3131 std::optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI); in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6175 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
6185 .addReg(MaskReg, MaskState) in expandPostRAPseudo()