| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 301 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
303 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
304 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
314 .addReg(MaskReg); in insertMaskedMerge()
332 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
374 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
473 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
489 .addReg(MaskReg); in expandAtomicMinMaxOp()
532 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
571 Register MaskReg, in tryToFoldBNEOnCmpXchgResult() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 238 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
240 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
241 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
249 .addReg(MaskReg); in insertMaskedMerge()
264 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
305 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
411 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
415 .addReg(MaskReg); in expandAtomicMinMaxOp()
462 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
467 MaskReg, ScratchReg); in expandAtomicMinMaxOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 100 void emitMask(MCRegister AddrReg, unsigned MaskReg, in emitMask() argument
106 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 232 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
233 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
234 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
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| H A D | LegalizerHelper.cpp | 9416 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
9431 Register MaskElt = MaskReg; in lowerSelect()
9445 MaskReg = ShufSplat.getReg(0); in lowerSelect()
9447 MaskReg = MaskElt; in lowerSelect()
9459 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
9460 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 597 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
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| H A D | AArch64InstrInfo.cpp | 1603 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr() argument
1605 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 5005 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
5006 unsigned MaskSize = MRI.getType(MaskReg).getSizeInBits(); in getInstrMapping()
5007 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
5022 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
5023 unsigned MaskSize = MRI.getType(MaskReg).getSizeInBits(); in getInstrMapping()
5024 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
5047 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
5048 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
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| H A D | AMDGPUInstructionSelector.cpp | 3093 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
3095 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
3101 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
3108 APInt MaskOnes = VT->getKnownOnes(MaskReg).zext(64); in selectG_PTRMASK()
3119 .addReg(MaskReg) in selectG_PTRMASK()
3136 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
3145 .addReg(MaskReg); in selectG_PTRMASK()
3173 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
3187 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13100 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
13176 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
13190 .addReg(MaskReg); in EmitPartwordAtomicBinary()
13191 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
13199 .addReg(MaskReg); in EmitPartwordAtomicBinary()
14120 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
14205 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
14210 .addReg(MaskReg); in EmitInstrWithCustomInserter()
14213 .addReg(MaskReg); in EmitInstrWithCustomInserter()
14221 .addReg(MaskReg); in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3265 Register MaskReg = I.getOperand(2).getReg(); in select() local
3266 std::optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6232 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
6242 .addReg(MaskReg, MaskState) in expandPostRAPseudo()
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