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Searched refs:MaskLo (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1366 SDValue MaskLo, MaskHi; in SplitMask()
1369 GetSplitVector(Mask, MaskLo, MaskHi); in SplitMask()
1371 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL); in SplitVecRes_BinOp()
1372 return std::make_pair(MaskLo, MaskHi); in SplitVecRes_BinOp()
1393 SDValue MaskLo, MaskHi; in SplitVecRes_BinOp()
1394 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(2)); in SplitVecRes_BinOp()
1401 {LHSLo, RHSLo, MaskLo, EVLLo}, Flags);
1427 SDValue MaskLo, MaskHi; in SplitVecRes_TernaryOp()
1428 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3)); in SplitVecRes_TernaryOp()
1435 {Op0Lo, Op1Lo, Op2Lo, MaskLo, EVLL in SplitVecRes_TernaryOp()
1362 SDValue MaskLo, MaskHi; SplitMask() local
1389 SDValue MaskLo, MaskHi; SplitVecRes_BinOp() local
1423 SDValue MaskLo, MaskHi; SplitVecRes_TernaryOp() local
2093 SDValue MaskLo, MaskHi; SplitVecRes_VP_LOAD() local
2249 SDValue MaskLo, MaskHi; SplitVecRes_MLOAD() local
2340 SDValue MaskLo, MaskHi; SplitVecRes_Gather() local
2446 SDValue MaskLo, MaskHi, EVLLo, EVLHi; SplitVecRes_SETCC() local
2488 SDValue MaskLo, MaskHi; SplitVecRes_UnaryOp() local
2607 SDValue MaskLo, MaskHi; SplitVecRes_ExtendOp() local
3373 SDValue MaskLo, MaskHi; SplitVecOp_VP_REDUCE() local
3413 SDValue MaskLo, MaskHi, EVLLo, EVLHi; SplitVecOp_UnaryOp() local
3636 SDValue MaskLo, MaskHi; SplitVecOp_VP_STORE() local
3789 SDValue MaskLo, MaskHi; SplitVecOp_MSTORE() local
3882 SDValue MaskLo, MaskHi; SplitVecOp_Scatter() local
4133 SDValue MaskLo, MaskHi, EVLLo, EVLHi; SplitVecOp_VSETCC() local
4173 SDValue MaskLo, MaskHi, EVLLo, EVLHi; SplitVecOp_FP_ROUND() local
[all...]
H A DLegalizeIntegerTypes.cpp1666 SDValue MaskLo, MaskHi, EVLLo, EVLHi; in PromoteIntRes_TRUNCATE() local
1667 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1)); in PromoteIntRes_TRUNCATE()
1670 EOp1 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp1, MaskLo, EVLLo); in PromoteIntRes_TRUNCATE()
H A DTargetLowering.cpp2405 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
2410 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) in SimplifyDemandedBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2975 Register MaskLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
2978 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo) in selectG_PTRMASK()
2982 .addReg(MaskLo); in selectG_PTRMASK()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6197 auto [MaskLo, MaskHi] = DAG.SplitVector(Op.getOperand(2), DL); in SplitVectorReductionOp()
6203 {Op.getOperand(0), Lo, MaskLo, EVLLo}, Op->getFlags()); in SplitVectorReductionOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23613 static const int MaskLo[] = {0, 0, 2, 2}; in LowerVSETCC() local
23614 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); in LowerVSETCC()
23639 static const int MaskLo[] = { 0, 0, 2, 2 }; in LowerVSETCC() local
23641 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); in LowerVSETCC()