| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 305 inline bool isShiftedMask_32(uint32_t Value, unsigned &MaskIdx, in isShiftedMask_32() argument
309 MaskIdx = llvm::countr_zero(Value); in isShiftedMask_32()
318 inline bool isShiftedMask_64(uint64_t Value, unsigned &MaskIdx, in isShiftedMask_64() argument
322 MaskIdx = llvm::countr_zero(Value); in isShiftedMask_64()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPISelLowering.cpp | 68 auto MaskIdx = ISD::getVPMaskIdx(Opcode); in lowerToVVP() local
70 if (MaskIdx) in lowerToVVP()
71 Mask = Op->getOperand(*MaskIdx); in lowerToVVP()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2302 // - MaskIdx where each byte is the corresponding index (for non-negative in LowerVECTOR_SHUFFLE()
2305 uint64_t MaskIdx = 0; in LowerVECTOR_SHUFFLE() local
2312 MaskIdx |= M << S; in LowerVECTOR_SHUFFLE()
2317 if (MaskIdx == (0x03020100 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2320 if (MaskIdx == (0x00010203 | MaskUnd)) { in LowerVECTOR_SHUFFLE()
2329 if (MaskIdx == (0x06040200 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2331 if (MaskIdx == (0x07050301 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2336 if (MaskIdx == (0x02000604 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2338 if (MaskIdx == (0x03010705 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2344 if (MaskIdx in LowerVECTOR_SHUFFLE()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVPseudos.td | 564 class RISCVMaskedPseudo<bits<4> MaskIdx, bit ActiveAffectsRes=false> {
567 bits<4> MaskOpIdx = MaskIdx;
1842 RISCVMaskedPseudo<MaskIdx=2>,
1860 RISCVMaskedPseudo<MaskIdx=2>,
1888 RISCVMaskedPseudo<MaskIdx=3>,
1918 RISCVMaskedPseudo<MaskIdx=3>,
2043 RISCVMaskedPseudo<MaskIdx=1>,
2068 RISCVMaskedPseudo<MaskIdx=2, ActiveAffectsRes=true>,
2105 RISCVMaskedPseudo<MaskIdx=3>;
2129 RISCVMaskedPseudo<MaskIdx
[all...] |
| H A D | RISCVInstrInfoZvk.td | 417 RISCVMaskedPseudo<MaskIdx=2>;
|
| H A D | RISCVISelLowering.cpp | 11255 auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode()); in lowerVPOp()
11256 if (MaskIdx) { in lowerVPOp()
11257 if (*MaskIdx == OpIdx.index()) in lowerVPOp()
11253 auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode()); lowerVPOp() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 594 unsigned MaskIdx, MaskLen;
596 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
597 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
602 unsigned MaskIdx, MaskLen;
604 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
605 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
606 return CurDAG->getTargetConstant(MaskIdx + MaskLen - 1, SDLoc(N),
612 unsigned MaskIdx, MaskLen;
614 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
615 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
[all …]
|
| H A D | LoongArchISelLowering.cpp | 3206 unsigned MaskIdx, MaskLen; in performSRLCombine() local
3213 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine()
3221 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
3224 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performSRLCombine()
3367 unsigned MaskIdx, MaskLen; in performORCombine() local
3370 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
3371 MaskIdx == 0 && (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(1))) && in performORCombine()
3394 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
3397 CNShamt->getZExtValue() == MaskIdx) { in performORCombine()
3403 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performORCombine()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 502 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() argument
504 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
511 MaskIdx = TrailZ; in isShiftedMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2216 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2217 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2223 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); in instCombineIntrinsic()
2260 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2261 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2266 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); in instCombineIntrinsic()
|
| H A D | X86ISelDAGToDAG.cpp | 2189 unsigned MaskIdx, MaskLen; in foldMaskAndShiftToScale() local
2190 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskAndShiftToScale()
2192 unsigned MaskLZ = 64 - (MaskIdx + MaskLen); in foldMaskAndShiftToScale()
2198 unsigned AMShiftAmt = MaskIdx; in foldMaskAndShiftToScale()
2288 unsigned MaskIdx, MaskLen; in foldMaskedShiftToBEXTR() local
2289 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskedShiftToBEXTR()
2296 unsigned AMShiftAmt = MaskIdx; in foldMaskedShiftToBEXTR()
|
| H A D | X86ISelLowering.cpp | 9631 int MaskIdx = Mask[i]; in isShuffleEquivalent() local
9633 if (0 <= MaskIdx && MaskIdx != ExpectedIdx) { in isShuffleEquivalent()
9634 SDValue MaskV = MaskIdx < Size ? V1 : V2; in isShuffleEquivalent()
9636 MaskIdx = MaskIdx < Size ? MaskIdx : (MaskIdx - Size); in isShuffleEquivalent()
9638 if (!IsElementEquivalent(Size, MaskV, ExpectedV, MaskIdx, ExpectedIdx)) in isShuffleEquivalent()
9682 int MaskIdx = Mask[i]; in isTargetShuffleEquivalent() local
9684 if (MaskIdx == SM_SentinelUndef || MaskIdx == ExpectedIdx) in isTargetShuffleEquivalent()
9686 if (MaskIdx == SM_SentinelZero) { in isTargetShuffleEquivalent()
9699 if (MaskIdx >= 0) { in isTargetShuffleEquivalent()
9700 SDValue MaskV = MaskIdx < Size ? V1 : V2; in isTargetShuffleEquivalent()
[all …]
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 3062 for (unsigned MaskIdx = 0; in emitBoolVecConversion() local
3063 MaskIdx < std::min<>(NumElementsDst, NumElementsSrc); ++MaskIdx) in emitBoolVecConversion()
3064 ShuffleMask[MaskIdx] = MaskIdx; in emitBoolVecConversion()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ComplexDeinterleavingPass.cpp | 499 int MaskIdx = Idx * 2; in isInterleavingMask() local
500 if (Mask[MaskIdx] != Idx || Mask[MaskIdx + 1] != (Idx + HalfNumElements)) in isInterleavingMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1888 const SDValue &MaskIdx = Op.getOperand(OpIdx + 1); in LowerIntrinsic() local
1889 if (MaskIdx.isUndef() || MaskIdx.getNode()->getAsZExtVal() >= 32) { in LowerIntrinsic()
1890 bool isTarget = MaskIdx.getNode()->getOpcode() == ISD::TargetConstant; in LowerIntrinsic()
1893 Ops[OpIdx++] = MaskIdx; in LowerIntrinsic()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 313 auto MaskIdx = [&](Value *Idx) { in foldCmpLoadFromIndexedGlobal() local
325 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
346 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
369 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
385 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
412 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4108 unsigned MaskIdx, MaskLen; in performSrlCombine() local
4109 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
4110 MaskIdx == ShiftAmt) { in performSrlCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12007 SDValue MaskIdx = MaskSource.getOperand(1); in ReconstructShuffleWithRuntimeMask() local
12008 if (!isa<ConstantSDNode>(MaskIdx) || in ReconstructShuffleWithRuntimeMask()
12009 !cast<ConstantSDNode>(MaskIdx)->getConstantIntValue()->equalsInt(i)) in ReconstructShuffleWithRuntimeMask()
17530 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
17531 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
17535 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
17536 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2843 int MaskIdx = MaskElt / NewElts; in SplitVecRes_VECTOR_SHUFFLE()
2844 if (OpIdx == MaskIdx) in SplitVecRes_VECTOR_SHUFFLE()
2839 int MaskIdx = MaskElt / NewElts; SplitVecRes_VECTOR_SHUFFLE() local
|
| H A D | DAGCombiner.cpp | 26791 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) in visitVPOp() local
26793 ISD::isConstantSplatVectorAllZeros(N->getOperand(*MaskIdx).getNode()); in visitVPOp()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13850 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13851 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13855 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13856 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
|