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Searched refs:MaskIdx (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h306 inline bool isShiftedMask_32(uint32_t Value, unsigned &MaskIdx, in isShiftedMask_32() argument
310 MaskIdx = llvm::countr_zero(Value); in isShiftedMask_32()
319 inline bool isShiftedMask_64(uint64_t Value, unsigned &MaskIdx, in isShiftedMask_64() argument
323 MaskIdx = llvm::countr_zero(Value); in isShiftedMask_64()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp68 auto MaskIdx = ISD::getVPMaskIdx(Opcode); in lowerToVVP() local
70 if (MaskIdx) in lowerToVVP()
71 Mask = Op->getOperand(*MaskIdx); in lowerToVVP()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2327 uint64_t MaskIdx = 0; in LowerVECTOR_SHUFFLE() local
2334 MaskIdx |= M << S; in LowerVECTOR_SHUFFLE()
2339 if (MaskIdx == (0x03020100 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2342 if (MaskIdx == (0x00010203 | MaskUnd)) { in LowerVECTOR_SHUFFLE()
2351 if (MaskIdx == (0x06040200 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2353 if (MaskIdx == (0x07050301 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2358 if (MaskIdx == (0x02000604 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2360 if (MaskIdx == (0x03010705 | MaskUnd)) in LowerVECTOR_SHUFFLE()
2366 if (MaskIdx == (0x0706050403020100ull | MaskUnd)) in LowerVECTOR_SHUFFLE()
2369 if (MaskIdx == (0x0001020304050607ull | MaskUnd)) { in LowerVECTOR_SHUFFLE()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td587 class RISCVMaskedPseudo<bits<4> MaskIdx> {
590 bits<4> MaskOpIdx = MaskIdx;
1865 RISCVMaskedPseudo<MaskIdx=2>,
1883 RISCVMaskedPseudo<MaskIdx=2>,
1911 RISCVMaskedPseudo<MaskIdx=3>,
1941 RISCVMaskedPseudo<MaskIdx=3>,
1959 RISCVMaskedPseudo<MaskIdx=2>,
1986 RISCVMaskedPseudo<MaskIdx=3>,
2013 RISCVMaskedPseudo<MaskIdx=3>,
2029 RISCVMaskedPseudo<MaskIdx=1>,
[all …]
H A DRISCVInstrInfoXAndes.td542 RISCVMaskedPseudo<MaskIdx=2>,
H A DRISCVInstrInfoZvk.td432 RISCVMaskedPseudo<MaskIdx=2>;
H A DRISCVISelLowering.cpp12980 auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode()); in lowerVPOp() local
12981 if (MaskIdx) { in lowerVPOp()
12982 if (*MaskIdx == OpIdx.index()) in lowerVPOp()
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h522 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() argument
524 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
531 MaskIdx = TrailZ; in isShiftedMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td633 unsigned MaskIdx, MaskLen;
635 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
636 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
641 unsigned MaskIdx, MaskLen;
643 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
644 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
645 return CurDAG->getTargetConstant(MaskIdx + MaskLen - 1, SDLoc(N),
651 unsigned MaskIdx, MaskLen;
653 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
654 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
[all …]
H A DLoongArchISelLowering.cpp4489 unsigned MaskIdx, MaskLen; in performSRLCombine() local
4496 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine()
4504 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
4507 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performSRLCombine()
4862 unsigned MaskIdx, MaskLen; in performORCombine() local
4865 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
4866 MaskIdx == 0 && (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(1))) && in performORCombine()
4889 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
4892 CNShamt->getZExtValue() == MaskIdx) { in performORCombine()
4898 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performORCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp697 int MaskIdx = Mask[Idx] % Sz; in processShuffleMasks() local
698 int SrcRegIdx = MaskIdx / SzSrc + (Mask[Idx] >= Sz ? NumOfSrcRegs : 0); in processShuffleMasks()
703 RegMasks[SrcRegIdx][K] = MaskIdx % SzSrc; in processShuffleMasks()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp2224 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2225 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2231 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); in instCombineIntrinsic()
2268 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2269 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2274 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); in instCombineIntrinsic()
H A DX86ISelDAGToDAG.cpp2247 unsigned MaskIdx, MaskLen; in foldMaskAndShiftToScale() local
2248 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskAndShiftToScale()
2250 unsigned MaskLZ = 64 - (MaskIdx + MaskLen); in foldMaskAndShiftToScale()
2256 unsigned AMShiftAmt = MaskIdx; in foldMaskAndShiftToScale()
2346 unsigned MaskIdx, MaskLen; in foldMaskedShiftToBEXTR() local
2347 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskedShiftToBEXTR()
2354 unsigned AMShiftAmt = MaskIdx; in foldMaskedShiftToBEXTR()
H A DX86ISelLowering.cpp10081 int MaskIdx = Mask[i]; in isShuffleEquivalent() local
10083 if (0 <= MaskIdx && MaskIdx != ExpectedIdx) { in isShuffleEquivalent()
10084 SDValue MaskV = MaskIdx < Size ? V1 : V2; in isShuffleEquivalent()
10086 MaskIdx = MaskIdx < Size ? MaskIdx : (MaskIdx - Size); in isShuffleEquivalent()
10088 if (!IsElementEquivalent(Size, MaskV, ExpectedV, MaskIdx, ExpectedIdx)) in isShuffleEquivalent()
10135 int MaskIdx = Mask[i]; in isTargetShuffleEquivalent() local
10137 if (MaskIdx == SM_SentinelUndef || MaskIdx == ExpectedIdx) in isTargetShuffleEquivalent()
10142 if (MaskIdx == SM_SentinelZero) { in isTargetShuffleEquivalent()
10155 if (MaskIdx >= 0) { in isTargetShuffleEquivalent()
10156 SDValue MaskV = MaskIdx < Size ? V1 : V2; in isTargetShuffleEquivalent()
[all …]
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCodeGenFunction.cpp3268 for (unsigned MaskIdx = 0; in emitBoolVecConversion() local
3269 MaskIdx < std::min<>(NumElementsDst, NumElementsSrc); ++MaskIdx) in emitBoolVecConversion()
3270 ShuffleMask[MaskIdx] = MaskIdx; in emitBoolVecConversion()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DComplexDeinterleavingPass.cpp515 int MaskIdx = Idx * 2; in isInterleavingMask() local
516 if (Mask[MaskIdx] != Idx || Mask[MaskIdx + 1] != (Idx + HalfNumElements)) in isInterleavingMask()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp786 unsigned MaskIdx = *ISD::getVPMaskIdx(Node->getOpcode()); in Promote() local
789 Node->getOperand(MaskIdx), Node->getOperand(EVLIdx)); in Promote()
808 unsigned MaskIdx = *ISD::getVPMaskIdx(Node->getOpcode()); in Promote() local
810 Node->getOperand(MaskIdx), Node->getOperand(EVLIdx)); in Promote()
H A DLegalizeVectorTypes.cpp2978 int MaskIdx = MaskElt / NewElts; in SplitVecRes_VECTOR_SHUFFLE() local
2979 if (OpIdx == MaskIdx) in SplitVecRes_VECTOR_SHUFFLE()
H A DDAGCombiner.cpp27905 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) in visitVPOp() local
27907 ISD::isConstantSplatVectorAllZeros(N->getOperand(*MaskIdx).getNode()); in visitVPOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2235 const SDValue &MaskIdx = Op.getOperand(OpIdx + 1); in LowerIntrinsic() local
2236 if (MaskIdx.isUndef() || MaskIdx.getNode()->getAsZExtVal() >= 32) { in LowerIntrinsic()
2237 bool isTarget = MaskIdx.getNode()->getOpcode() == ISD::TargetConstant; in LowerIntrinsic()
2240 Ops[OpIdx++] = MaskIdx; in LowerIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCompares.cpp311 auto MaskIdx = [&](Value *Idx) { in foldCmpLoadFromIndexedGlobal() local
323 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
344 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
367 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
383 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
410 Idx = MaskIdx(Idx); in foldCmpLoadFromIndexedGlobal()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp4278 unsigned MaskIdx, MaskLen; in performSrlCombine() local
4279 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
4280 MaskIdx == RHSVal) { in performSrlCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12874 SDValue MaskIdx = MaskSource.getOperand(1); in ReconstructShuffleWithRuntimeMask() local
12875 if (!isa<ConstantSDNode>(MaskIdx) || in ReconstructShuffleWithRuntimeMask()
12876 !cast<ConstantSDNode>(MaskIdx)->getConstantIntValue()->equalsInt(i)) in ReconstructShuffleWithRuntimeMask()
17959 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
17960 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
17964 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
17965 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13925 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13926 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13930 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13931 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()