| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1434 SDValue MaskLo, MaskHi; in SplitMask() local
1437 GetSplitVector(Mask, MaskLo, MaskHi); in SplitMask()
1439 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL); in SplitMask()
1440 return std::make_pair(MaskLo, MaskHi); in SplitMask()
1461 SDValue MaskLo, MaskHi; in SplitVecRes_BinOp() local
1462 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(2)); in SplitVecRes_BinOp()
1471 {LHSHi, RHSHi, MaskHi, EVLHi}, Flags); in SplitVecRes_BinOp()
1495 SDValue MaskLo, MaskHi; in SplitVecRes_TernaryOp() local
1496 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3)); in SplitVecRes_TernaryOp()
1505 {Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags); in SplitVecRes_TernaryOp()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1711 SDValue MaskLo, MaskHi, EVLLo, EVLHi; in PromoteIntRes_TRUNCATE() local
1712 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1)); in PromoteIntRes_TRUNCATE()
1716 EOp2 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp2, MaskHi, EVLHi); in PromoteIntRes_TRUNCATE()
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| H A D | TargetLowering.cpp | 2474 APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
2481 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) in SimplifyDemandedBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 3183 Register MaskHi = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
3186 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskHi) in selectG_PTRMASK()
3190 .addReg(MaskHi); in selectG_PTRMASK()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 24352 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
24353 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
24363 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
24364 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
24402 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
24404 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi); in LowerVSETCC()
24406 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 7166 auto [MaskLo, MaskHi] = DAG.SplitVector(Op.getOperand(2), DL); in SplitVectorReductionOp()
7174 {ResLo, Hi, MaskHi, EVLHi}, Op->getFlags()); in SplitVectorReductionOp()
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