| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.h | 41 MachineRegisterInfo &MRI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | AMDGPURegisterBankInfo.h | 53 MachineRegisterInfo &MRI,
60 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
90 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
100 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI,
106 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
111 const MachineRegisterInfo &MRI,
116 const MachineRegisterInfo &MRI,
121 const MachineRegisterInfo &MRI,
139 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
145 const MachineInstr &MI, const MachineRegisterInfo
[all...] |
| H A D | SILowerI1Copies.h | 35 Register createLaneMaskReg(MachineRegisterInfo *MRI,
36 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs);
49 MachineRegisterInfo *MRI = nullptr;
52 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
77 initializeLaneMaskRegisterAttributes(MachineRegisterInfo::VRegAttrs Attrs) { in initializeLaneMaskRegisterAttributes()
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| H A D | GCNRegPressure.h | 27 class MachineRegisterInfo; variable
82 const MachineRegisterInfo &MRI);
196 bool isSaveBeneficial(Register Reg, const MachineRegisterInfo &MRI) const;
199 void saveReg(Register Reg, LaneBitmask Mask, const MachineRegisterInfo &MRI) { in saveReg()
272 mutable const MachineRegisterInfo *MRI = nullptr;
286 void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_);
301 const MachineRegisterInfo &MRI);
313 void reset(const MachineRegisterInfo &MRI, SlotIndex SI) { in reset()
427 const MachineRegisterInfo &MRI,
431 const MachineRegisterInfo &MRI,
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| H A D | SIRegisterInfo.h | 235 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
314 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI,
319 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
322 getRegClassForOperandReg(const MachineRegisterInfo &MRI,
325 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
326 bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
327 bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const { in isVectorRegister()
339 bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI,
378 const MachineRegisterInfo &MRI) const override;
403 MachineRegisterInfo &MRI,
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| H A D | AMDGPUGlobalISelUtils.h | 18 class MachineRegisterInfo; variable
30 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
42 MachineRegisterInfo &MRI;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 43 class MachineRegisterInfo; variable
96 LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI,
111 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
127 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
148 MachineRegisterInfo &MRI);
153 const MachineRegisterInfo &MRI);
181 getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI);
185 getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI);
189 const MachineRegisterInfo &MRI);
202 const MachineRegisterInfo &MRI,
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| H A D | MIPatternMatch.h | 28 [[nodiscard]] bool mi_match(Reg R, const MachineRegisterInfo &MRI, in mi_match()
34 [[nodiscard]] bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, in mi_match()
41 const MachineRegisterInfo &MRI, Pattern &&P) { in mi_match()
50 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
64 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
76 const MachineRegisterInfo &);
80 const MachineRegisterInfo &MRI) { in matchConstant()
86 const MachineRegisterInfo &MRI) { in matchConstant()
93 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
111 const MachineRegisterInfo &);
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| H A D | LoadStoreOpt.h | 36 class MachineRegisterInfo; variable
59 LLVM_ABI BaseIndexOffset getPointerInfo(Register Ptr, MachineRegisterInfo &MRI);
66 MachineRegisterInfo &MRI);
73 MachineRegisterInfo &MRI, AliasAnalysis *AA);
87 MachineRegisterInfo *MRI = nullptr;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 41 void MachineRegisterInfo::Delegate::anchor() {} in anchor()
43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) in MachineRegisterInfo() function in MachineRegisterInfo
58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass()
84 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
122 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass()
145 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { in createIncompleteVirtualRegister()
156 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.h | 37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeICMP(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeFunnelShift(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeCTPOP(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeAtomicCmpxchg128(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | AArch64PostLegalizerLowering.cpp | 153 bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV()
189 bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN()
210 bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP()
226 bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip()
244 MachineRegisterInfo &MRI, in matchDupFromInsertVectorElt()
284 MachineRegisterInfo &MRI, in matchDupFromBuildVector()
305 bool matchDup(MachineInstr &MI, MachineRegisterInfo &MRI, in matchDup()
351 bool matchEXT(MachineInstr &MI, MachineRegisterInfo &MRI, in matchEXT()
407 void applyFullRev(MachineInstr &MI, MachineRegisterInfo &MRI) { in applyFullRev()
420 bool matchNonConstInsert(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchNonConstInsert()
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| H A D | AArch64GlobalISelUtils.h | 35 getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI);
41 const MachineRegisterInfo &MRI);
46 const MachineRegisterInfo &MRI);
60 extractPtrauthBlendDiscriminators(Register Disc, MachineRegisterInfo &MRI);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86LegalizerInfo.h | 40 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
43 bool legalizeFPTOUI(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeUITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeNarrowingStore(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeSITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeFPTOSI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeGETROUNDING(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | X86InstructionSelector.cpp | 80 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
96 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
98 bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
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| H A D | X86RegisterBankInfo.h | 55 const MachineRegisterInfo &MRI, const bool isFP,
69 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
74 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
78 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 28 class MachineRegisterInfo; variable
139 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
142 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
145 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
148 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
151 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
154 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
157 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
160 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
163 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 46 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass()
58 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
110 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
163 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands()
202 MachineRegisterInfo &MRI) { in canReplaceReg()
223 const MachineRegisterInfo &MRI) { in isTriviallyDead()
295 const MachineRegisterInfo &MRI) { in getIConstantVRegVal()
306 const MachineRegisterInfo &MRI) { in getIConstantFromReg()
314 llvm::getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI) { in getIConstantVRegSExtVal()
336 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, in getConstantVRegValWithLookThrough()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 42 MachineRegisterInfo &MRI) { in IsRegInClass()
52 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
56 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
60 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
64 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
68 bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSSReg()
76 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVRegisterBankInfo.h | 41 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
45 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
49 bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI,
53 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 63 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
66 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
69 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
71 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
73 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
130 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr()
178 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift()
192 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate()
227 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI, in processDstReg()
288 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI, in processInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 66 MachineRegisterInfo *MRI;
103 const MachineRegisterInfo *MRI) { in isGPR64()
112 const MachineRegisterInfo *MRI) { in isFPR64()
126 const MachineRegisterInfo *MRI, in getSrcFromCopy()
207 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
220 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
239 for (MachineRegisterInfo::use_instr_nodbg_iterator in isProfitableToTransform()
300 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
319 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVUtils.h | 34 class MachineRegisterInfo; variable
130 std::string getStringValueFromReg(Register Reg, MachineRegisterInfo &MRI);
239 const MachineRegisterInfo *MRI);
242 uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI);
450 MachineInstr *getVRegDef(MachineRegisterInfo &MRI, Register Reg);
460 SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI,
464 MachineRegisterInfo *MRI,
503 MachineInstr *passCopy(MachineInstr *Def, const MachineRegisterInfo *MRI);
504 MachineInstr *getDef(const MachineOperand &MO, const MachineRegisterInfo *MRI);
505 MachineInstr *getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI);
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 33 class MachineRegisterInfo; variable
291 MachineRegisterInfo &MRI;
325 MachineRegisterInfo &MRI);
336 MachineRegisterInfo &getMRI() const { return MRI; } in getMRI()
556 const MachineRegisterInfo &MRI) const;
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
667 MachineRegisterInfo &MRI);
752 TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
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