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Searched refs:MVT (Results 1 – 25 of 303) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp267 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty); in getArithmeticInstrCost()
273 (LT.second.getScalarType() == MVT::i32 || in getArithmeticInstrCost()
274 LT.second.getScalarType() == MVT::i64)) { in getArithmeticInstrCost()
286 LT.second.getScalarType() == MVT::i32) { in getArithmeticInstrCost()
301 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); in getArithmeticInstrCost()
307 if (ST->useSLMArithCosts() && LT.second == MVT::v4i32) { in getArithmeticInstrCost()
321 if (!SignedMode && OpMinSize <= 32 && LT.second.getScalarType() == MVT::i64) in getArithmeticInstrCost()
374 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
375 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
376 { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
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H A DX86ISelLowering.cpp136 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); in X86TargetLowering()
147 setOperationAction(ISD::CLEAR_CACHE, MVT::Other, Expand); in X86TargetLowering()
181 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
182 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
183 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
185 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
187 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
188 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
191 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
192 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h36 class MVT {
58 constexpr MVT() = default;
59 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() function
61 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
62 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
63 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
64 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
65 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
66 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
76 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp180 case MVT::bf16: return "bf16"; in getEVTString()
181 case MVT::ppcf128: return "ppcf128"; in getEVTString()
182 case MVT::isVoid: return "isVoid"; in getEVTString()
183 case MVT::Other: return "ch"; in getEVTString()
184 case MVT::Glue: return "glue"; in getEVTString()
185 case MVT::x86mmx: return "x86mmx"; in getEVTString()
186 case MVT::x86amx: return "x86amx"; in getEVTString()
187 case MVT::i64x8: return "i64x8"; in getEVTString()
188 case MVT::Metadata: return "Metadata"; in getEVTString()
189 case MVT::Untyped: return "Untyped"; in getEVTString()
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H A DTargetLoweringBase.cpp110 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
111 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
112 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
113 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
114 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
121 if (OpVT == MVT::f16) { in getFPEXT()
122 if (RetVT == MVT::f32) in getFPEXT()
124 if (RetVT == MVT::f64) in getFPEXT()
126 if (RetVT == MVT::f80) in getFPEXT()
128 if (RetVT == MVT::f128) in getFPEXT()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp514 return (EltVT == MVT::f32 && ST->hasVFP2Base()) || in getCastInstrCost()
515 (EltVT == MVT::f64 && ST->hasFP64()) || in getCastInstrCost()
516 (EltVT == MVT::f16 && ST->hasFullFP16()); in getCastInstrCost()
543 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
544 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
545 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
546 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
547 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
548 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
549 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
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H A DARMCallingConv.h20 bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
23 bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
26 bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
29 bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
32 bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
35 bool CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
38 bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
41 bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
44 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
47 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
H A DARMCallingConv.cpp20 static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, in f64AssignAPCS()
48 static bool CC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in CC_ARM_APCS_Custom_f64()
54 if (LocVT == MVT::v2f64 && in CC_ARM_APCS_Custom_f64()
61 static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, in f64AssignAAPCS()
101 static bool CC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in CC_ARM_AAPCS_Custom_f64()
107 if (LocVT == MVT::v2f64 && in CC_ARM_AAPCS_Custom_f64()
113 static bool f64RetAssign(unsigned ValNo, MVT ValVT, MVT LocVT, in f64RetAssign()
133 static bool RetCC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in RetCC_ARM_APCS_Custom_f64()
139 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) in RetCC_ARM_APCS_Custom_f64()
144 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in RetCC_ARM_AAPCS_Custom_f64()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp23 MVT WebAssembly::parseMVT(StringRef Type) { in parseMVT()
24 return StringSwitch<MVT>(Type) in parseMVT()
25 .Case("i32", MVT::i32) in parseMVT()
26 .Case("i64", MVT::i64) in parseMVT()
27 .Case("f32", MVT::f32) in parseMVT()
28 .Case("f64", MVT::f64) in parseMVT()
29 .Case("i64", MVT::i64) in parseMVT()
30 .Case("v16i8", MVT::v16i8) in parseMVT()
31 .Case("v8i16", MVT::v8i16) in parseMVT()
32 .Case("v4i32", MVT::v4i32) in parseMVT()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp150 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64); in SelectAddrModeIndexedUImm()
207 Res2 = CurDAG->getTargetConstant(ShtAmt, SDLoc(N), MVT::i32); in SelectRoundingVLShr()
249 template<MVT::SimpleValueType VT>
254 template <MVT::SimpleValueType VT, bool Negate>
259 template <MVT::SimpleValueType VT>
264 template <MVT::SimpleValueType VT, bool Invert = false>
269 template <MVT::SimpleValueType VT>
304 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectCntImm()
320 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectEXTImm()
335 Imm = CurDAG->getRegister(BaseReg + C, MVT::Other); in ImmToReg()
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H A DAArch64TargetTransformInfo.cpp601 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
602 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
603 MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, in getIntrinsicInstrCost()
604 MVT::nxv2i64}; in getIntrinsicInstrCost()
607 if (LT.second == MVT::v2i64) in getIntrinsicInstrCost()
609 if (any_of(ValidMinMaxTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
617 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
618 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
619 MVT::v2i64}; in getIntrinsicInstrCost()
625 if (any_of(ValidSatTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
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H A DAArch64CallingConvention.h19 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
22 bool CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
46 bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
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H A DAArch64FastISel.cpp180 bool isTypeLegal(Type *Ty, MVT &VT);
181 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
185 bool simplifyAddress(Address &Addr, MVT VT);
194 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
199 Register emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
202 Register emitAddSub_rr(bool UseAdd, MVT RetVT, Register LHSReg,
205 Register emitAddSub_ri(bool UseAdd, MVT RetVT, Register LHSReg, uint64_t Imm,
207 Register emitAddSub_rs(bool UseAdd, MVT RetVT, Register LHSReg,
211 Register emitAddSub_rx(bool UseAdd, MVT RetVT, Register LHSReg,
219 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp83 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
85 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
87 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
90 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
92 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
94 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
97 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
99 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
101 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
104 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in INITIALIZE_PASS()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp46 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
75 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
79 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
81 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
82 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
85 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
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H A DR600ISelLowering.cpp32 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
45 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
50 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
51 setLoadExtAction(Op, VT, MVT::i1, Promote); in R600TargetLowering()
52 setLoadExtAction(Op, VT, MVT::i8, Custom); in R600TargetLowering()
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H A DSIISelLowering.cpp95 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
96 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
98 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
99 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
101 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
106 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering()
107 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering()
108 addRegisterClass(MVT::Untyped, V64RegClass); in SITargetLowering()
110 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
111 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp34 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
35 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
36 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
37 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
39 static std::tuple<unsigned, unsigned, unsigned> getIEEEProperties(MVT Ty) { in getIEEEProperties()
41 MVT ElemTy = Ty.getScalarType(); in getIEEEProperties()
43 case MVT::f16: in getIEEEProperties()
45 case MVT::f32: in getIEEEProperties()
47 case MVT::f64: in getIEEEProperties()
58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
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H A DHexagonISelLowering.cpp138 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
162 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
164 bool isBoolVector = VT.getVectorElementType() == MVT::i1; in getVectorTypeBreakdownForCallingConv()
171 RegisterVT = MVT::v8i8; in getVectorTypeBreakdownForCallingConv()
172 IntermediateVT = MVT::v8i1; in getVectorTypeBreakdownForCallingConv()
180 RegisterVT = MVT::v64i8; in getVectorTypeBreakdownForCallingConv()
181 IntermediateVT = MVT::v64i1; in getVectorTypeBreakdownForCallingConv()
190 RegisterVT = MVT::v128i8; in getVectorTypeBreakdownForCallingConv()
191 IntermediateVT = MVT::v128i1; in getVectorTypeBreakdownForCallingConv()
200 std::pair<MVT, unsigned>
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp46 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
47 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
59 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
60 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
85 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
86 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
109 static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, in Analyze_CC_Sparc64_Full()
110 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in Analyze_CC_Sparc64_Full()
112 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in Analyze_CC_Sparc64_Full()
117 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in Analyze_CC_Sparc64_Full()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp163 static bool IsPTXVectorType(MVT VT) { in IsPTXVectorType()
167 case MVT::v2i1: in IsPTXVectorType()
168 case MVT::v4i1: in IsPTXVectorType()
169 case MVT::v2i8: in IsPTXVectorType()
170 case MVT::v4i8: in IsPTXVectorType()
171 case MVT::v8i8: // <2 x i8x4> in IsPTXVectorType()
172 case MVT::v16i8: // <4 x i8x4> in IsPTXVectorType()
173 case MVT::v2i16: in IsPTXVectorType()
174 case MVT::v4i16: in IsPTXVectorType()
175 case MVT::v8i16: // <4 x i16x2> in IsPTXVectorType()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp47 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
59 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
60 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
64 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
65 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
67 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
68 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
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H A DWebAssemblyFastISel.cpp113 MVT::SimpleValueType getSimpleType(Type *Ty) { in getSimpleType()
116 : MVT::INVALID_SIMPLE_VALUE_TYPE; in getSimpleType()
118 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { in getLegalType()
120 case MVT::i1: in getLegalType()
121 case MVT::i8: in getLegalType()
122 case MVT::i16: in getLegalType()
123 return MVT::i32; in getLegalType()
124 case MVT::i32: in getLegalType()
125 case MVT::i64: in getLegalType()
126 case MVT::f32: in getLegalType()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.h22 bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_PPC64_ELF(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
H A DPPCFastISel.cpp106 Register fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
135 bool isTypeLegal(Type *Ty, MVT &VT);
136 bool isLoadTypeLegal(Type *Ty, MVT &VT);
153 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
156 bool PPCEmitStore(MVT VT, Register SrcReg, Address &Addr);
159 bool PPCEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, Register DestReg,
161 Register PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
162 Register PPCMaterializeGV(const GlobalValue *GV, MVT VT);
163 Register PPCMaterializeInt(const ConstantInt *CI, MVT VT,
167 Register PPCMoveToIntReg(const Instruction *I, MVT VT, Register SrcReg,
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