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Searched refs:MUX (Results 1 – 25 of 67) sorted by relevance

123

/freebsd/sys/dev/clk/rockchip/
H A Drk3568_cru.c303 MUX(USB480M, "usb480m", mux_usb480m_p, 0, -16, 14, 2),
326 MUX(0, "sclk_core_pre_sel", sclk_core_pre_p, 0, 2, 15, 1),
351 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux_sel", clk_gpu_pre_mux_p, 0, 6, 11, 1),
357 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 0, 7,
360 MUX(CLK_NPU, "clk_npu", clk_npu_p, 0, 7, 15, 1),
371 MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, RK_CLK_COMPOSITE_GRF, 9,
376 MUX(0, "aclk_perimid_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 10, 4, 2),
377 MUX(0, "hclk_perimid_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 6, 2),
378 MUX(0, "aclk_gic_audio_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 10, 8, 2),
379 MUX(0, "hclk_gic_audio_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 10, 2),
[all …]
H A Drk3568_pmucru.c111 MUX(0, "clk_rtc_32k_mux", clk_rtc32k_pmu_p, 0, 0, 6, 2),
118 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, 2, 15, 1),
125 MUX(0, "sclk_uart0_div_sel", sclk_uart0_div_p, 0, 4, 8, 2),
126 MUX(0, "sclk_uart0_mux", sclk_uart0_p, 0, 4, 10, 2),
133 MUX(0, "clk_pwm0_sel", clk_pwm0_p, 0, 6, 7, 1),
134 MUX(0, "dbclk_gpio0_sel", xin24m_32k_p, 0, 6, 15, 1),
140 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, 8, 0, 1),
141 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, 8, 1, 1),
142 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, 8, 2, 1),
143 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, 8, 3, 1),
[all …]
H A Drk3399_cru.c875 MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
881 MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
901 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,
903 MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,
911 MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,
913 MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,
961 MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,
967 MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,
973 MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,
979 MUX(0, "clk_i2sout_c", i2sout_p, 0,
[all …]
H A Drk3288_cru.c611 MUX(SCLK_UART4, "sclk_uart4", uart4_p, 0,
617 MUX(0, "i2s_pre", i2s_pre_p, 0,
619 MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0,
625 MUX(0, "spdif_src", cpll_gpll_p, 0,
627 MUX(0, "spdif_mux", spdif_p, 0,
669 MUX(0, "uart_src", cpll_gpll_p, 0,
671 MUX(0, "usbphy480m_src_s", usbphy480m_p, 0,
673 MUX(SCLK_UART0, "sclk_uart0", uart0_p, 0,
679 MUX(SCLK_UART1, "sclk_uart1", uart1_p, 0,
686 MUX(SCLK_UART2, "sclk_uart2", uart2_p, 0,
[all …]
H A Drk3328_cru.c882 MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2),
889 MUX(0, "clk_i2s1_mux", mux_i2s1_p, RK_CLK_MUX_REPARENT, 8, 8, 2),
897 MUX(0, "clk_i2s2_mux", mux_i2s2_p, RK_CLK_MUX_REPARENT, 10, 8, 2),
905 MUX(0, "clk_spdif_pll", pll_src_cpll_gpll_p, 0, 12, 15, 1),
906 MUX(SCLK_SPDIF, "clk_spdif", mux_spdif_p, 0, 12, 8, 2),
913 MUX(0, "clk_uart0_pll", pll_src_cpll_gpll_usb480m_p, 0, 14, 12, 2),
914 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, 0, 14, 8, 2),
921 MUX(0, "clk_uart1_pll", pll_src_cpll_gpll_usb480m_p, 0, 16, 12, 2),
922 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, 0, 16, 8, 2),
929 MUX(0, "clk_uart2_pll", pll_src_cpll_gpll_usb480m_p, 0, 18, 12, 2),
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mq_ccm.c136 MUX(IMX8MQ_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x28, 16, 2),
137 MUX(IMX8MQ_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x18, 16, 2),
138 MUX(IMX8MQ_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x20, 16, 2),
139 MUX(IMX8MQ_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x0, 16, 2),
140 MUX(IMX8MQ_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x8, 16, 2),
141 MUX(IMX8MQ_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x10, 16, 2),
142 MUX(IMX8MQ_SYS3_PLL1_REF_SEL, "sys3_pll1_ref_sel", pll_ref_p, 0, 0x48, 0, 2),
143 MUX(IMX8MQ_DRAM_PLL1_REF_SEL, "dram_pll1_ref_sel", pll_ref_p, 0, 0x60, 0, 2),
144 MUX(IMX8MQ_VIDEO2_PLL1_REF_SEL, "video2_pll1_ref_sel", pll_ref_p, 0, 0x54, 0, 2),
161 MUX(IMX8MQ_ARM_PLL_BYPASS, "arm_pll_bypass", arm_pll_bypass_p, 0, 0x28, 14, 1),
[all …]
H A Dimx8mp_ccm.c359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
368 MUX(IMX8MP_SYS_PLL3_REF_SEL, "sys_pll3_ref_sel", pll_ref_p, 0, 0x114, 0, 2),
[all …]
/freebsd/sys/arm64/qoriq/clk/
H A Dlx2160a_clkgen.c117 #define MUX(_id1, _id2, cname, plist, o) \ macro
130 MUX(QORIQ_TYPE_CMUX, 0, "cg-cmux0", cmuxa_plist, 0x70000);
132 MUX(QORIQ_TYPE_CMUX, 1, "cg-cmux1", cmuxa_plist, 0x70020);
134 MUX(QORIQ_TYPE_CMUX, 2, "cg-cmux2", cmuxa_plist, 0x70040);
136 MUX(QORIQ_TYPE_CMUX, 3, "cg-cmux3", cmuxa_plist, 0x70060);
138 MUX(QORIQ_TYPE_CMUX, 4, "cg-cmux4", cmuxb_plist, 0x70080);
140 MUX(QORIQ_TYPE_CMUX, 5, "cg-cmux5", cmuxb_plist, 0x700A0);
142 MUX(QORIQ_TYPE_CMUX, 6, "cg-cmux6", cmuxb_plist, 0x700C0);
144 MUX(QORIQ_TYPE_CMUX, 7, "cg-cmux7", cmuxb_plist, 0x700E0);
/freebsd/contrib/bearssl/src/int/
H A Di32_div32.c38 hi = MUX(ch, 0, hi); in br_divrem()
48 hi = MUX(ctl, hi2, hi); in br_divrem()
49 lo = MUX(ctl, lo2, lo); in br_divrem()
54 *r = MUX(cf, lo - d, lo); in br_divrem()
H A Di32_muladd.c95 q = MUX(EQ(a0, b0), 0xFFFFFFFF, MUX(EQ(g, 0), 0, g - 1)); in br_i32_muladd_small()
120 tb = MUX(EQ(nxw, mw), tb, GT(nxw, mw)); in br_i32_muladd_small()
H A Di31_muladd.c115 q = MUX(EQ(a0, b0), 0x7FFFFFFF, MUX(EQ(g, 0), 0, g - 1)); in br_i31_muladd_small()
141 tb = MUX(EQ(nxw, mw), tb, GT(nxw, mw)); in br_i31_muladd_small()
H A Di15_bitlen.c40 tw = MUX(c, w, tw); in br_i15_bit_length()
41 twk = MUX(c, (uint32_t)xlen, twk); in br_i15_bit_length()
H A Di31_bitlen.c40 tw = MUX(c, w, tw); in br_i31_bit_length()
41 twk = MUX(c, (uint32_t)xlen, twk); in br_i31_bit_length()
H A Di32_bitlen.c40 tw = MUX(c, w, tw); in br_i32_bit_length()
41 twk = MUX(c, (uint32_t)xlen, twk); in br_i32_bit_length()
H A Di15_decmod.c98 r = MUX(EQ(cc, 0), r, cc); in br_i15_decode_mod()
102 r = MUX(EQ(xw, 0), r, 1); in br_i15_decode_mod()
H A Di31_decmod.c98 r = MUX(EQ(cc, 0), r, cc); in br_i31_decode_mod()
102 r = MUX(EQ(xw, 0), r, 1); in br_i31_decode_mod()
H A Di15_muladd.c134 q = MUX(EQ(b, a0), 0x7FFF, q - 1 + ((q - 1) >> 31)); in br_i15_muladd_small()
159 tb = MUX(EQ(nxw, mw), tb, GT(nxw, mw)); in br_i15_muladd_small()
H A Di31_ninv31.c38 return MUX(x & 1, -y, 0) & 0x7FFFFFFF; in br_i31_ninv31()
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_car.c64 #define MUX(_id, cname, plists, o, s, w) \ macro
226 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
227 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
228 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
229 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
230 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
233 MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1),
234 MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
237 MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
238 MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1),
/freebsd/contrib/bearssl/src/mac/
H A Dhmac_ct.c174 x0 = MUX(EQ(u, (uint32_t)len), 0x80, d); in br_hmac_outCT()
175 x1 = MUX(LT(u, kl), 0x00, e); in br_hmac_outCT()
176 x[0] = MUX(LE(u, (uint32_t)len), x0, x1); in br_hmac_outCT()
/freebsd/contrib/bearssl/src/ssl/
H A Dssl_rec_cbc.c89 tmp[u] = MUX(ctl, buf[v], buf[u]); in cond_rotate()
143 len = MUX(good, (uint32_t)(max_len - pad_len), min_len); in cbc_decrypt()
169 tmp1[v] |= MUX(GE(u, len_nomac) & LT(u, len_withmac), in cbc_decrypt()
171 rot_count = MUX(EQ(u, len_nomac), v, rot_count); in cbc_decrypt()
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-mux-gpmux.txt11 | .------. | .------+ child bus A, on MUX value set to 0
13 | '------' | '--+---+ child bus B, on MUX value set to 1
15 | | MUX- | | | | | |
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.txt26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
/freebsd/contrib/bearssl/src/symcipher/
H A Dpoly1305_ctmulq.c425 v0 = MUX(ctl, v0 + 5, v0); in br_poly1305_ctmulq_run()
426 v1 = MUX(ctl, 0, v1); in br_poly1305_ctmulq_run()
427 v2 = MUX(ctl, 0, v2); in br_poly1305_ctmulq_run()
428 v3 = MUX(ctl, 0, v3); in br_poly1305_ctmulq_run()
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Drockchip,pinctrl.txt58 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
59 The MUX 0 means gpio and MUX 1 to N mean the specific device function.

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