| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 66 case ISD::MSTORE: in getVVPOpcode()
203 case ISD::MSTORE: in getMaskPos()
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| H A D | VEISelLowering.cpp | 344 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE}) in initVPUActions()
1927 case ISD::MSTORE: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1402 MSTORE, enumerator
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| H A D | SelectionDAGNodes.h | 1515 case ISD::MSTORE:
1562 case ISD::MSTORE:
2847 N->getOpcode() == ISD::MSTORE;
2888 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2910 return N->getOpcode() == ISD::MSTORE;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 142 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
182 setOperationAction(ISD::MSTORE, P, Custom); in initializeHVXLowering()
227 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
295 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
392 setOperationAction(ISD::MSTORE, BoolW, Custom); in initializeHVXLowering()
2215 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
3021 uint64_t MemSize = (MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE) in SplitHvxMemOp()
3045 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
3068 if (MemOpc == ISD::MSTORE) { in SplitHvxMemOp()
3189 case ISD::MSTORE: in LowerHvxOperation()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 454 case ISD::MSTORE: return "masked_store"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 3434 case ISD::MSTORE: in SplitVectorOperand()
6827 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break; in WidenVectorOperand()
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| H A D | SelectionDAG.cpp | 893 case ISD::MSTORE: { in AddNodeIDCustom()
10236 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
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| H A D | LegalizeDAG.cpp | 1209 case ISD::MSTORE: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 2000 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N), in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 2028 case ISD::MSTORE: return visitMSTORE(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 804 def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 920 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1098 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1175 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
1345 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
1435 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
8037 case ISD::MSTORE: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1149 setTargetDAGCombine(ISD::MSTORE); in AArch64TargetLowering()
1637 setOperationAction(ISD::MSTORE, VT, Custom); in AArch64TargetLowering()
2318 setOperationAction(ISD::MSTORE, VT, Default); in addTypeForFixedLengthSVE()
7412 case ISD::MSTORE: in LowerOperation()
23593 assert((N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::MSTORE) && in foldTruncStoreOfExt()
26812 case ISD::MSTORE: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1455 case ISD::MSTORE: in SelectT2AddrModeImm7Offset()
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| H A D | ARMISelLowering.cpp | 282 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
356 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1655 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1885 setOperationAction(ISD::MSTORE, VT, Custom); in X86TargetLowering()
2058 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
2065 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
2222 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2671 ISD::MSTORE, in X86TargetLowering()
33723 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG); in LowerOperation()
60536 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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