1 /*
2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
4 * Support: freebsdraid@avagotech.com
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer. 2. Redistributions
12 * in binary form must reproduce the above copyright notice, this list of
13 * conditions and the following disclaimer in the documentation and/or other
14 * materials provided with the distribution. 3. Neither the name of the
15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or
16 * promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing
33 * official policies,either expressed or implied, of the FreeBSD Project.
34 *
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
37 *
38 */
39
40 #include <sys/cdefs.h>
41 #ifndef MRSAS_H
42 #define MRSAS_H
43
44 #include <sys/param.h> /* defines used in kernel.h */
45 #include <sys/module.h>
46 #include <sys/systm.h>
47 #include <sys/proc.h>
48 #include <sys/errno.h>
49 #include <sys/kernel.h> /* types used in module initialization */
50 #include <sys/conf.h> /* cdevsw struct */
51 #include <sys/uio.h> /* uio struct */
52 #include <sys/malloc.h>
53 #include <sys/bus.h> /* structs, prototypes for pci bus
54 * stuff */
55 #include <sys/rman.h>
56 #include <sys/types.h>
57 #include <sys/lock.h>
58 #include <sys/mutex.h>
59 #include <sys/sema.h>
60 #include <sys/sysctl.h>
61 #include <sys/stat.h>
62 #include <sys/taskqueue.h>
63 #include <sys/poll.h>
64 #include <sys/selinfo.h>
65
66 #include <machine/bus.h>
67 #include <machine/resource.h>
68 #include <machine/atomic.h>
69
70 #include <dev/pci/pcivar.h> /* For pci_get macros! */
71 #include <dev/pci/pcireg.h>
72
73 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool"
74
75 /*
76 * Device IDs and PCI
77 */
78 #define MRSAS_TBOLT 0x005b
79 #define MRSAS_INVADER 0x005d
80 #define MRSAS_FURY 0x005f
81 #define MRSAS_INTRUDER 0x00ce
82 #define MRSAS_INTRUDER_24 0x00cf
83 #define MRSAS_CUTLASS_52 0x0052
84 #define MRSAS_CUTLASS_53 0x0053
85 /* Gen3.5 Conroller */
86 #define MRSAS_VENTURA 0x0014
87 #define MRSAS_CRUSADER 0x0015
88 #define MRSAS_HARPOON 0x0016
89 #define MRSAS_TOMCAT 0x0017
90 #define MRSAS_VENTURA_4PORT 0x001B
91 #define MRSAS_CRUSADER_4PORT 0x001C
92 #define MRSAS_AERO_10E0 0x10E0
93 #define MRSAS_AERO_10E1 0x10E1
94 #define MRSAS_AERO_10E2 0x10E2
95 #define MRSAS_AERO_10E3 0x10E3
96 #define MRSAS_AERO_10E4 0x10E4
97 #define MRSAS_AERO_10E5 0x10E5
98 #define MRSAS_AERO_10E6 0x10E6
99 #define MRSAS_AERO_10E7 0x10E7
100
101 /*
102 * Firmware State Defines
103 */
104 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF
105 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000
106 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1
107
108 /*
109 * Message Frame Defines
110 */
111 #define MRSAS_SENSE_LEN 96
112 #define MRSAS_FUSION_MAX_RESET_TRIES 3
113
114 /*
115 * Miscellaneous Defines
116 */
117 #define BYTE_ALIGNMENT 1
118 #define MRSAS_MAX_NAME_LENGTH 32
119 #define MRSAS_VERSION "07.709.04.00-fbsd"
120 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
121 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */
122 #define DONE 0
123 #define MRSAS_PAGE_SIZE 4096
124 #define MRSAS_RESET_NOTICE_INTERVAL 5
125 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */
126 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */
127 #define THRESHOLD_REPLY_COUNT 50
128 #define MAX_MSIX_COUNT 128
129
130 #define MAX_STREAMS_TRACKED 8
131 #define MR_STREAM_BITMAP 0x76543210
132 #define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */
133 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
134 #define ZERO_LAST_STREAM 0x0fffffff
135
136 /*
137 * Boolean types
138 */
139 enum err {
140 SUCCESS, FAIL
141 };
142
143 MALLOC_DECLARE(M_MRSAS);
144 SYSCTL_DECL(_hw_mrsas);
145
146 #define MRSAS_INFO (1 << 0)
147 #define MRSAS_TRACE (1 << 1)
148 #define MRSAS_FAULT (1 << 2)
149 #define MRSAS_OCR (1 << 3)
150 #define MRSAS_TOUT MRSAS_OCR
151 #define MRSAS_AEN (1 << 4)
152 #define MRSAS_PRL11 (1 << 5)
153
154 #define mrsas_dprint(sc, level, msg, args...) \
155 do { \
156 if (sc->mrsas_debug & level) \
157 device_printf(sc->mrsas_dev, msg, ##args); \
158 } while (0)
159
160 #define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0)
161 #define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x)); } while (0)
162
163 /****************************************************************************
164 * Raid Context structure which describes MegaRAID specific IO Paramenters
165 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
166 ****************************************************************************/
167
168 typedef struct _RAID_CONTEXT {
169 #if _BYTE_ORDER == _LITTLE_ENDIAN
170 u_int8_t Type:4;
171 u_int8_t nseg:4;
172 #else
173 u_int8_t nseg:4;
174 u_int8_t Type:4;
175 #endif
176 u_int8_t resvd0;
177 u_int16_t timeoutValue;
178 u_int8_t regLockFlags;
179 u_int8_t resvd1;
180 u_int16_t VirtualDiskTgtId;
181 u_int64_t regLockRowLBA;
182 u_int32_t regLockLength;
183 u_int16_t nextLMId;
184 u_int8_t exStatus;
185 u_int8_t status;
186 u_int8_t RAIDFlags;
187 u_int8_t numSGE;
188 u_int16_t configSeqNum;
189 u_int8_t spanArm;
190 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */
191 u_int8_t numSGEExt; /* 0x1E 1M IO support */
192 u_int8_t resvd2; /* 0x1F */
193 } RAID_CONTEXT;
194
195 /*
196 * Raid Context structure which describes ventura MegaRAID specific IO Paramenters
197 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
198 */
199 typedef struct _RAID_CONTEXT_G35 {
200 #if _BYTE_ORDER == _LITTLE_ENDIAN
201 u_int16_t Type:4;
202 u_int16_t nseg:4;
203 u_int16_t resvd0:8;
204 #else
205 u_int16_t resvd0:8;
206 u_int16_t nseg:4;
207 u_int16_t Type:4;
208 #endif
209 u_int16_t timeoutValue;
210 union {
211 struct {
212 #if _BYTE_ORDER == _LITTLE_ENDIAN
213 u_int16_t reserved:1;
214 u_int16_t sld:1;
215 u_int16_t c2f:1;
216 u_int16_t fwn:1;
217 u_int16_t sqn:1;
218 u_int16_t sbs:1;
219 u_int16_t rw:1;
220 u_int16_t log:1;
221 u_int16_t cpuSel:4;
222 u_int16_t setDivert:4;
223 #else
224 u_int16_t setDivert:4;
225 u_int16_t cpuSel:4;
226 u_int16_t log:1;
227 u_int16_t rw:1;
228 u_int16_t sbs:1;
229 u_int16_t sqn:1;
230 u_int16_t fwn:1;
231 u_int16_t c2f:1;
232 u_int16_t sld:1;
233 u_int16_t reserved:1;
234 #endif
235 } bits;
236 u_int16_t s;
237 } routingFlags;
238 u_int16_t VirtualDiskTgtId;
239 u_int64_t regLockRowLBA;
240 u_int32_t regLockLength;
241 union {
242 u_int16_t nextLMId;
243 u_int16_t peerSMID;
244 } smid;
245 u_int8_t exStatus;
246 u_int8_t status;
247 u_int8_t RAIDFlags;
248 u_int8_t spanArm;
249 u_int16_t configSeqNum;
250 #if _BYTE_ORDER == _LITTLE_ENDIAN
251 u_int16_t numSGE:12;
252 u_int16_t reserved:3;
253 u_int16_t streamDetected:1;
254 #else
255 u_int16_t streamDetected:1;
256 u_int16_t reserved:3;
257 u_int16_t numSGE:12;
258 #endif
259 u_int8_t resvd2[2];
260 } RAID_CONTEXT_G35;
261
262 typedef union _RAID_CONTEXT_UNION {
263 RAID_CONTEXT raid_context;
264 RAID_CONTEXT_G35 raid_context_g35;
265 } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION;
266
267 /*************************************************************************
268 * MPI2 Defines
269 ************************************************************************/
270
271 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
272 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
273 #define MPI2_VERSION_MAJOR (0x02)
274 #define MPI2_VERSION_MINOR (0x00)
275 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
276 #define MPI2_VERSION_MAJOR_SHIFT (8)
277 #define MPI2_VERSION_MINOR_MASK (0x00FF)
278 #define MPI2_VERSION_MINOR_SHIFT (0)
279 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
280 MPI2_VERSION_MINOR)
281 #define MPI2_HEADER_VERSION_UNIT (0x10)
282 #define MPI2_HEADER_VERSION_DEV (0x00)
283 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
284 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
285 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
286 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
287 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
288 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
289 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
290 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
291 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
293 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
294 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
295 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
296 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
297 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
298 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
299 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
300 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
301 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
302 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
303 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
304 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
305 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
306 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
307 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
308 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
309 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
310 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
311 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
312 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
313 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
314 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
315
316 #ifndef MPI2_POINTER
317 #define MPI2_POINTER *
318 #endif
319
320 /***************************************
321 * MPI2 Structures
322 ***************************************/
323
324 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
325 u_int64_t Address;
326 u_int32_t Length;
327 u_int16_t Reserved1;
328 u_int8_t NextChainOffset;
329 u_int8_t Flags;
330 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
331 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
332
333 typedef struct _MPI2_SGE_SIMPLE_UNION {
334 u_int32_t FlagsLength;
335 union {
336 u_int32_t Address32;
337 u_int64_t Address64;
338 } u;
339 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
340 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
341
342 typedef struct {
343 u_int8_t CDB[20]; /* 0x00 */
344 u_int32_t PrimaryReferenceTag; /* 0x14 */
345 u_int16_t PrimaryApplicationTag;/* 0x18 */
346 u_int16_t PrimaryApplicationTagMask; /* 0x1A */
347 u_int32_t TransferLength; /* 0x1C */
348 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
349 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
350
351 typedef struct _MPI2_SGE_CHAIN_UNION {
352 u_int16_t Length;
353 u_int8_t NextChainOffset;
354 u_int8_t Flags;
355 union {
356 u_int32_t Address32;
357 u_int64_t Address64;
358 } u;
359 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
360 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
361
362 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
363 u_int32_t Address;
364 u_int32_t FlagsLength;
365 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
366 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
367 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
368 u_int64_t Address;
369 u_int32_t Length;
370 u_int16_t Reserved1;
371 u_int8_t Reserved2;
372 u_int8_t Flags;
373 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
374 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
375
376 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
377 MPI2_IEEE_SGE_SIMPLE32 Simple32;
378 MPI2_IEEE_SGE_SIMPLE64 Simple64;
379 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
380 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
381
382 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
383 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
384
385 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
386 MPI2_IEEE_SGE_CHAIN32 Chain32;
387 MPI2_IEEE_SGE_CHAIN64 Chain64;
388 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
389 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
390
391 typedef union _MPI2_SGE_IO_UNION {
392 MPI2_SGE_SIMPLE_UNION MpiSimple;
393 MPI2_SGE_CHAIN_UNION MpiChain;
394 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
395 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
396 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
397 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
398
399 typedef union {
400 u_int8_t CDB32[32];
401 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
402 MPI2_SGE_SIMPLE_UNION SGE;
403 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
404 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
405
406 /****************************************************************************
407 * * SCSI Task Management messages
408 * ****************************************************************************/
409
410 /*SCSI Task Management Request Message */
411 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST {
412 u_int16_t DevHandle; /*0x00 */
413 u_int8_t ChainOffset; /*0x02 */
414 u_int8_t Function; /*0x03 */
415 u_int8_t Reserved1; /*0x04 */
416 u_int8_t TaskType; /*0x05 */
417 u_int8_t Reserved2; /*0x06 */
418 u_int8_t MsgFlags; /*0x07 */
419 u_int8_t VP_ID; /*0x08 */
420 u_int8_t VF_ID; /*0x09 */
421 u_int16_t Reserved3; /*0x0A */
422 u_int8_t LUN[8]; /*0x0C */
423 u_int32_t Reserved4[7]; /*0x14 */
424 u_int16_t TaskMID; /*0x30 */
425 u_int16_t Reserved5; /*0x32 */
426 } MPI2_SCSI_TASK_MANAGE_REQUEST;
427
428 /*SCSI Task Management Reply Message */
429 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY {
430 u_int16_t DevHandle; /*0x00 */
431 u_int8_t MsgLength; /*0x02 */
432 u_int8_t Function; /*0x03 */
433 u_int8_t ResponseCode; /*0x04 */
434 u_int8_t TaskType; /*0x05 */
435 u_int8_t Reserved1; /*0x06 */
436 u_int8_t MsgFlags; /*0x07 */
437 u_int8_t VP_ID; /*0x08 */
438 u_int8_t VF_ID; /*0x09 */
439 u_int16_t Reserved2; /*0x0A */
440 u_int16_t Reserved3; /*0x0C */
441 u_int16_t IOCStatus; /*0x0E */
442 u_int32_t IOCLogInfo; /*0x10 */
443 u_int32_t TerminationCount; /*0x14 */
444 u_int32_t ResponseInfo; /*0x18 */
445 } MPI2_SCSI_TASK_MANAGE_REPLY;
446
447 typedef struct _MR_TM_REQUEST {
448 char request[128];
449 } MR_TM_REQUEST;
450
451 typedef struct _MR_TM_REPLY {
452 char reply[128];
453 } MR_TM_REPLY;
454
455 /* SCSI Task Management Request Message */
456 typedef struct _MR_TASK_MANAGE_REQUEST {
457 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
458 MR_TM_REQUEST TmRequest;
459 union {
460 struct {
461 #if _BYTE_ORDER == _LITTLE_ENDIAN
462 u_int32_t isTMForLD:1;
463 u_int32_t isTMForPD:1;
464 u_int32_t reserved1:30;
465 #else
466 u_int32_t reserved1:30;
467 u_int32_t isTMForPD:1;
468 u_int32_t isTMForLD:1;
469 #endif
470 u_int32_t reserved2;
471 } tmReqFlags;
472 MR_TM_REPLY TMReply;
473 } uTmReqReply;
474 } MR_TASK_MANAGE_REQUEST;
475
476 /* TaskType values */
477 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
478 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
479 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
480 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
481 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
482 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
483 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
484 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
485 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
486
487 /* ResponseCode values */
488 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
489 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
490 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
491 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
492 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
493 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
494 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
495 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
496
497 /*
498 * RAID SCSI IO Request Message Total SGE count will be one less than
499 * _MPI2_SCSI_IO_REQUEST
500 */
501 typedef struct _MPI2_RAID_SCSI_IO_REQUEST {
502 u_int16_t DevHandle; /* 0x00 */
503 u_int8_t ChainOffset; /* 0x02 */
504 u_int8_t Function; /* 0x03 */
505 u_int16_t Reserved1; /* 0x04 */
506 u_int8_t Reserved2; /* 0x06 */
507 u_int8_t MsgFlags; /* 0x07 */
508 u_int8_t VP_ID; /* 0x08 */
509 u_int8_t VF_ID; /* 0x09 */
510 u_int16_t Reserved3; /* 0x0A */
511 u_int32_t SenseBufferLowAddress;/* 0x0C */
512 u_int16_t SGLFlags; /* 0x10 */
513 u_int8_t SenseBufferLength; /* 0x12 */
514 u_int8_t Reserved4; /* 0x13 */
515 u_int8_t SGLOffset0; /* 0x14 */
516 u_int8_t SGLOffset1; /* 0x15 */
517 u_int8_t SGLOffset2; /* 0x16 */
518 u_int8_t SGLOffset3; /* 0x17 */
519 u_int32_t SkipCount; /* 0x18 */
520 u_int32_t DataLength; /* 0x1C */
521 u_int32_t BidirectionalDataLength; /* 0x20 */
522 u_int16_t IoFlags; /* 0x24 */
523 u_int16_t EEDPFlags; /* 0x26 */
524 u_int32_t EEDPBlockSize; /* 0x28 */
525 u_int32_t SecondaryReferenceTag;/* 0x2C */
526 u_int16_t SecondaryApplicationTag; /* 0x30 */
527 u_int16_t ApplicationTagTranslationMask; /* 0x32 */
528 u_int8_t LUN[8]; /* 0x34 */
529 u_int32_t Control; /* 0x3C */
530 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
531 RAID_CONTEXT_UNION RaidContext; /* 0x60 */
532 MPI2_SGE_IO_UNION SGL; /* 0x80 */
533 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
534 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
535
536 /*
537 * MPT RAID MFA IO Descriptor.
538 */
539 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
540 u_int32_t RequestFlags:8;
541 u_int32_t MessageAddress1:24; /* bits 31:8 */
542 u_int32_t MessageAddress2; /* bits 61:32 */
543 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
544
545 /* Default Request Descriptor */
546 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
547 u_int8_t RequestFlags; /* 0x00 */
548 u_int8_t MSIxIndex; /* 0x01 */
549 u_int16_t SMID; /* 0x02 */
550 u_int16_t LMID; /* 0x04 */
551 u_int16_t DescriptorTypeDependent; /* 0x06 */
552 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
553
554 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
555 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
556
557 /* High Priority Request Descriptor */
558 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
559 u_int8_t RequestFlags; /* 0x00 */
560 u_int8_t MSIxIndex; /* 0x01 */
561 u_int16_t SMID; /* 0x02 */
562 u_int16_t LMID; /* 0x04 */
563 u_int16_t Reserved1; /* 0x06 */
564 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
565
566 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
567 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
568
569 /* SCSI IO Request Descriptor */
570 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
571 u_int8_t RequestFlags; /* 0x00 */
572 u_int8_t MSIxIndex; /* 0x01 */
573 u_int16_t SMID; /* 0x02 */
574 u_int16_t LMID; /* 0x04 */
575 u_int16_t DevHandle; /* 0x06 */
576 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
577
578 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
579 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
580
581 /* SCSI Target Request Descriptor */
582 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
583 u_int8_t RequestFlags; /* 0x00 */
584 u_int8_t MSIxIndex; /* 0x01 */
585 u_int16_t SMID; /* 0x02 */
586 u_int16_t LMID; /* 0x04 */
587 u_int16_t IoIndex; /* 0x06 */
588 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
589
590 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
591 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
592
593 /* RAID Accelerator Request Descriptor */
594 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
595 u_int8_t RequestFlags; /* 0x00 */
596 u_int8_t MSIxIndex; /* 0x01 */
597 u_int16_t SMID; /* 0x02 */
598 u_int16_t LMID; /* 0x04 */
599 u_int16_t Reserved; /* 0x06 */
600 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
601
602 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
603 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
604
605 /* union of Request Descriptors */
606 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION {
607 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
608 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
609 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
610 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
611 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
612 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
613 union {
614 struct {
615 u_int32_t low;
616 u_int32_t high;
617 } u;
618 u_int64_t Words;
619 } addr;
620 } MRSAS_REQUEST_DESCRIPTOR_UNION;
621
622 /* Default Reply Descriptor */
623 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
624 u_int8_t ReplyFlags; /* 0x00 */
625 u_int8_t MSIxIndex; /* 0x01 */
626 u_int16_t DescriptorTypeDependent1; /* 0x02 */
627 u_int32_t DescriptorTypeDependent2; /* 0x04 */
628 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
629 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
630
631 /* Address Reply Descriptor */
632 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
633 u_int8_t ReplyFlags; /* 0x00 */
634 u_int8_t MSIxIndex; /* 0x01 */
635 u_int16_t SMID; /* 0x02 */
636 u_int32_t ReplyFrameAddress; /* 0x04 */
637 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
638 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
639
640 /* SCSI IO Success Reply Descriptor */
641 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
642 u_int8_t ReplyFlags; /* 0x00 */
643 u_int8_t MSIxIndex; /* 0x01 */
644 u_int16_t SMID; /* 0x02 */
645 u_int16_t TaskTag; /* 0x04 */
646 u_int16_t Reserved1; /* 0x06 */
647 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
648
649 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
650 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
651
652 /* TargetAssist Success Reply Descriptor */
653 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
654 u_int8_t ReplyFlags; /* 0x00 */
655 u_int8_t MSIxIndex; /* 0x01 */
656 u_int16_t SMID; /* 0x02 */
657 u_int8_t SequenceNumber; /* 0x04 */
658 u_int8_t Reserved1; /* 0x05 */
659 u_int16_t IoIndex; /* 0x06 */
660 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
661
662 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
663 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
664
665 /* Target Command Buffer Reply Descriptor */
666 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
667 u_int8_t ReplyFlags; /* 0x00 */
668 u_int8_t MSIxIndex; /* 0x01 */
669 u_int8_t VP_ID; /* 0x02 */
670 u_int8_t Flags; /* 0x03 */
671 u_int16_t InitiatorDevHandle; /* 0x04 */
672 u_int16_t IoIndex; /* 0x06 */
673 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
674
675 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
676 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
677
678 /* RAID Accelerator Success Reply Descriptor */
679 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
680 u_int8_t ReplyFlags; /* 0x00 */
681 u_int8_t MSIxIndex; /* 0x01 */
682 u_int16_t SMID; /* 0x02 */
683 u_int32_t Reserved; /* 0x04 */
684 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
685
686 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
687 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
688
689 /* union of Reply Descriptors */
690 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
691 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
692 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
693 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
694 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
695 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
696 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
697 u_int64_t Words;
698 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
699 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
700
701 typedef union {
702 volatile unsigned int val;
703 unsigned int val_rdonly;
704 } mrsas_atomic_t;
705
706 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val)
707 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
708 #define mrsas_atomic_dec(v) atomic_subtract_int(&(v)->val, 1)
709 #define mrsas_atomic_inc(v) atomic_add_int(&(v)->val, 1)
710
711 static inline int
mrsas_atomic_inc_return(mrsas_atomic_t * v)712 mrsas_atomic_inc_return(mrsas_atomic_t *v)
713 {
714 return 1 + atomic_fetchadd_int(&(v)->val, 1);
715 }
716
717 /* IOCInit Request message */
718 typedef struct _MPI2_IOC_INIT_REQUEST {
719 u_int8_t WhoInit; /* 0x00 */
720 u_int8_t Reserved1; /* 0x01 */
721 u_int8_t ChainOffset; /* 0x02 */
722 u_int8_t Function; /* 0x03 */
723 u_int16_t Reserved2; /* 0x04 */
724 u_int8_t Reserved3; /* 0x06 */
725 u_int8_t MsgFlags; /* 0x07 */
726 u_int8_t VP_ID; /* 0x08 */
727 u_int8_t VF_ID; /* 0x09 */
728 u_int16_t Reserved4; /* 0x0A */
729 u_int16_t MsgVersion; /* 0x0C */
730 u_int16_t HeaderVersion; /* 0x0E */
731 u_int32_t Reserved5; /* 0x10 */
732 u_int16_t Reserved6; /* 0x14 */
733 u_int8_t HostPageSize; /* 0x16 */
734 u_int8_t HostMSIxVectors; /* 0x17 */
735 u_int16_t Reserved8; /* 0x18 */
736 u_int16_t SystemRequestFrameSize; /* 0x1A */
737 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
738 u_int16_t ReplyFreeQueueDepth; /* 0x1E */
739 u_int32_t SenseBufferAddressHigh; /* 0x20 */
740 u_int32_t SystemReplyAddressHigh; /* 0x24 */
741 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */
742 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */
743 u_int64_t ReplyFreeQueueAddress;/* 0x38 */
744 u_int64_t TimeStamp; /* 0x40 */
745 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
746 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
747
748 /*
749 * MR private defines
750 */
751 #define MR_PD_INVALID 0xFFFF
752 #define MR_DEVHANDLE_INVALID 0xFFFF
753 #define MAX_SPAN_DEPTH 8
754 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
755 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
756 #define MAX_ROW_SIZE 32
757 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
758 #define MAX_LOGICAL_DRIVES 64
759 #define MAX_LOGICAL_DRIVES_EXT 256
760 #define MAX_LOGICAL_DRIVES_DYN 512
761
762 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
763 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
764
765 #define MAX_ARRAYS 128
766 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
767
768 #define MAX_ARRAYS_EXT 256
769 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT
770 #define MAX_API_ARRAYS_DYN 512
771
772 #define MAX_PHYSICAL_DEVICES 256
773 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
774 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
775 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
776 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
777 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100
778
779 #define MR_DCMD_PD_GET_INFO 0x02020000
780 #define MRSAS_MAX_PD_CHANNELS 1
781 #define MRSAS_MAX_LD_CHANNELS 1
782 #define MRSAS_MAX_DEV_PER_CHANNEL 256
783 #define MRSAS_DEFAULT_INIT_ID -1
784 #define MRSAS_MAX_LUN 8
785 #define MRSAS_DEFAULT_CMD_PER_LUN 256
786 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \
787 MRSAS_MAX_DEV_PER_CHANNEL)
788 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \
789 MRSAS_MAX_DEV_PER_CHANNEL)
790
791 #define VD_EXT_DEBUG 0
792 #define TM_DEBUG 1
793
794 /*******************************************************************
795 * RAID map related structures
796 ********************************************************************/
797 #pragma pack(1)
798 typedef struct _MR_DEV_HANDLE_INFO {
799 u_int16_t curDevHdl;
800 u_int8_t validHandles;
801 u_int8_t interfaceType;
802 u_int16_t devHandle[2];
803 } MR_DEV_HANDLE_INFO;
804
805 #pragma pack()
806
807 typedef struct _MR_ARRAY_INFO {
808 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
809 } MR_ARRAY_INFO;
810
811 typedef struct _MR_QUAD_ELEMENT {
812 u_int64_t logStart;
813 u_int64_t logEnd;
814 u_int64_t offsetInSpan;
815 u_int32_t diff;
816 u_int32_t reserved1;
817 } MR_QUAD_ELEMENT;
818
819 typedef struct _MR_SPAN_INFO {
820 u_int32_t noElements;
821 u_int32_t reserved1;
822 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
823 } MR_SPAN_INFO;
824
825 typedef struct _MR_LD_SPAN_ {
826 u_int64_t startBlk;
827 u_int64_t numBlks;
828 u_int16_t arrayRef;
829 u_int8_t spanRowSize;
830 u_int8_t spanRowDataSize;
831 u_int8_t reserved[4];
832 } MR_LD_SPAN;
833
834 typedef struct _MR_SPAN_BLOCK_INFO {
835 u_int64_t num_rows;
836 MR_LD_SPAN span;
837 MR_SPAN_INFO block_span_info;
838 } MR_SPAN_BLOCK_INFO;
839
840 typedef struct _MR_LD_RAID {
841 struct {
842 #if _BYTE_ORDER == _LITTLE_ENDIAN
843 u_int32_t fpCapable:1;
844 u_int32_t raCapable:1;
845 u_int32_t reserved5:2;
846 u_int32_t ldPiMode:4;
847 u_int32_t pdPiMode:4;
848 u_int32_t encryptionType:8;
849 u_int32_t fpWriteCapable:1;
850 u_int32_t fpReadCapable:1;
851 u_int32_t fpWriteAcrossStripe:1;
852 u_int32_t fpReadAcrossStripe:1;
853 u_int32_t fpNonRWCapable:1;
854 u_int32_t tmCapable:1;
855 u_int32_t fpCacheBypassCapable:1;
856 u_int32_t reserved4:5;
857 #else
858 u_int32_t reserved4:5;
859 u_int32_t fpCacheBypassCapable:1;
860 u_int32_t tmCapable:1;
861 u_int32_t fpNonRWCapable:1;
862 u_int32_t fpReadAcrossStripe:1;
863 u_int32_t fpWriteAcrossStripe:1;
864 u_int32_t fpReadCapable:1;
865 u_int32_t fpWriteCapable:1;
866 u_int32_t encryptionType:8;
867 u_int32_t pdPiMode:4;
868 u_int32_t ldPiMode:4;
869 u_int32_t reserved5:2;
870 u_int32_t raCapable:1;
871 u_int32_t fpCapable:1;
872 #endif
873 } capability;
874 u_int32_t reserved6;
875 u_int64_t size;
876
877 u_int8_t spanDepth;
878 u_int8_t level;
879 u_int8_t stripeShift;
880 u_int8_t rowSize;
881
882 u_int8_t rowDataSize;
883 u_int8_t writeMode;
884 u_int8_t PRL;
885 u_int8_t SRL;
886
887 u_int16_t targetId;
888 u_int8_t ldState;
889 u_int8_t regTypeReqOnWrite;
890 u_int8_t modFactor;
891 u_int8_t regTypeReqOnRead;
892 u_int16_t seqNum;
893
894 struct {
895 #if _BYTE_ORDER == _LITTLE_ENDIAN
896 u_int32_t reserved:30;
897 u_int32_t regTypeReqOnReadLsValid:1;
898 u_int32_t ldSyncRequired:1;
899 #else
900 u_int32_t ldSyncRequired:1;
901 u_int32_t regTypeReqOnReadLsValid:1;
902 u_int32_t reserved:30;
903 #endif
904 } flags;
905
906 u_int8_t LUN[8];
907 u_int8_t fpIoTimeoutForLd;
908 u_int8_t reserved2[3];
909 u_int32_t logicalBlockLength;
910 struct {
911 #if _BYTE_ORDER == _LITTLE_ENDIAN
912 u_int32_t reserved1:24;
913 u_int32_t LdLogicalBlockExp:4;
914 u_int32_t LdPiExp:4;
915 #else
916 u_int32_t LdPiExp:4;
917 u_int32_t LdLogicalBlockExp:4;
918 u_int32_t reserved1:24;
919 #endif
920 } exponent;
921 u_int8_t reserved3[0x80 - 0x38];
922 } MR_LD_RAID;
923
924 typedef struct _MR_LD_SPAN_MAP {
925 MR_LD_RAID ldRaid;
926 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE];
927 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
928 } MR_LD_SPAN_MAP;
929
930 typedef struct _MR_FW_RAID_MAP {
931 u_int32_t totalSize;
932 union {
933 struct {
934 u_int32_t maxLd;
935 u_int32_t maxSpanDepth;
936 u_int32_t maxRowSize;
937 u_int32_t maxPdCount;
938 u_int32_t maxArrays;
939 } validationInfo;
940 u_int32_t version[5];
941 u_int32_t reserved1[5];
942 } raid_desc;
943 u_int32_t ldCount;
944 u_int32_t Reserved1;
945
946 /*
947 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For
948 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD,
949 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
950 * 0x0,.....]. This is to help reduce the entire strcture size if
951 * there are few LDs or driver is looking info for 1 LD only.
952 */
953 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS];
954 u_int8_t fpPdIoTimeoutSec;
955 u_int8_t reserved2[7];
956 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
957 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
958 MR_LD_SPAN_MAP ldSpanMap[1];
959 } MR_FW_RAID_MAP;
960
961 typedef struct _MR_FW_RAID_MAP_EXT {
962 /* Not used in new map */
963 u_int32_t reserved;
964
965 union {
966 struct {
967 u_int32_t maxLd;
968 u_int32_t maxSpanDepth;
969 u_int32_t maxRowSize;
970 u_int32_t maxPdCount;
971 u_int32_t maxArrays;
972 } validationInfo;
973 u_int32_t version[5];
974 u_int32_t reserved1[5];
975 } fw_raid_desc;
976
977 u_int8_t fpPdIoTimeoutSec;
978 u_int8_t reserved2[7];
979
980 u_int16_t ldCount;
981 u_int16_t arCount;
982 u_int16_t spanCount;
983 u_int16_t reserve3;
984
985 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
986 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
987 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
988 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
989 } MR_FW_RAID_MAP_EXT;
990
991 typedef struct _MR_DRV_RAID_MAP {
992 /*
993 * Total size of this structure, including this field. This field
994 * will be manupulated by driver for ext raid map, else pick the
995 * value from firmware raid map.
996 */
997 u_int32_t totalSize;
998
999 union {
1000 struct {
1001 u_int32_t maxLd;
1002 u_int32_t maxSpanDepth;
1003 u_int32_t maxRowSize;
1004 u_int32_t maxPdCount;
1005 u_int32_t maxArrays;
1006 } validationInfo;
1007 u_int32_t version[5];
1008 u_int32_t reserved1[5];
1009 } drv_raid_desc;
1010
1011 /* timeout value used by driver in FP IOs */
1012 u_int8_t fpPdIoTimeoutSec;
1013 u_int8_t reserved2[7];
1014
1015 u_int16_t ldCount;
1016 u_int16_t arCount;
1017 u_int16_t spanCount;
1018 u_int16_t reserve3;
1019
1020 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1021 u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1022 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1023 MR_LD_SPAN_MAP ldSpanMap[1];
1024
1025 } MR_DRV_RAID_MAP;
1026
1027 /*
1028 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is
1029 * created to sync with old raid. And it is mainly for code re-use purpose.
1030 */
1031
1032 #pragma pack(1)
1033 typedef struct _MR_DRV_RAID_MAP_ALL {
1034 MR_DRV_RAID_MAP raidMap;
1035 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1036 } MR_DRV_RAID_MAP_ALL;
1037
1038 #pragma pack()
1039
1040 typedef struct _LD_LOAD_BALANCE_INFO {
1041 u_int8_t loadBalanceFlag;
1042 u_int8_t reserved1;
1043 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1044 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
1045 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
1046
1047 /* SPAN_SET is info caclulated from span info from Raid map per ld */
1048 typedef struct _LD_SPAN_SET {
1049 u_int64_t log_start_lba;
1050 u_int64_t log_end_lba;
1051 u_int64_t span_row_start;
1052 u_int64_t span_row_end;
1053 u_int64_t data_strip_start;
1054 u_int64_t data_strip_end;
1055 u_int64_t data_row_start;
1056 u_int64_t data_row_end;
1057 u_int8_t strip_offset[MAX_SPAN_DEPTH];
1058 u_int32_t span_row_data_width;
1059 u_int32_t diff;
1060 u_int32_t reserved[2];
1061 } LD_SPAN_SET, *PLD_SPAN_SET;
1062
1063 typedef struct LOG_BLOCK_SPAN_INFO {
1064 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1065 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1066
1067 #pragma pack(1)
1068 typedef struct _MR_FW_RAID_MAP_ALL {
1069 MR_FW_RAID_MAP raidMap;
1070 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1071 } MR_FW_RAID_MAP_ALL;
1072
1073 #pragma pack()
1074
1075 struct IO_REQUEST_INFO {
1076 u_int64_t ldStartBlock;
1077 u_int32_t numBlocks;
1078 u_int16_t ldTgtId;
1079 u_int8_t isRead;
1080 u_int16_t devHandle;
1081 u_int8_t pdInterface;
1082 u_int64_t pdBlock;
1083 u_int8_t fpOkForIo;
1084 u_int8_t IoforUnevenSpan;
1085 u_int8_t start_span;
1086 u_int8_t reserved;
1087 u_int64_t start_row;
1088 /* span[7:5], arm[4:0] */
1089 u_int8_t span_arm;
1090 u_int8_t pd_after_lb;
1091 boolean_t raCapable;
1092 u_int16_t r1_alt_dev_handle;
1093 };
1094
1095 /*
1096 * define MR_PD_CFG_SEQ structure for system PDs
1097 */
1098 struct MR_PD_CFG_SEQ {
1099 u_int16_t seqNum;
1100 u_int16_t devHandle;
1101 struct {
1102 #if _BYTE_ORDER == _LITTLE_ENDIAN
1103 u_int8_t tmCapable:1;
1104 u_int8_t reserved:7;
1105 #else
1106 u_int8_t reserved:7;
1107 u_int8_t tmCapable:1;
1108 #endif
1109 } capability;
1110 u_int8_t reserved;
1111 u_int16_t pdTargetId;
1112 } __packed;
1113
1114 struct MR_PD_CFG_SEQ_NUM_SYNC {
1115 u_int32_t size;
1116 u_int32_t count;
1117 struct MR_PD_CFG_SEQ seq[1];
1118 } __packed;
1119
1120 typedef struct _STREAM_DETECT {
1121 u_int64_t nextSeqLBA;
1122 struct megasas_cmd_fusion *first_cmd_fusion;
1123 struct megasas_cmd_fusion *last_cmd_fusion;
1124 u_int32_t countCmdsInStream;
1125 u_int16_t numSGEsInGroup;
1126 u_int8_t isRead;
1127 u_int8_t groupDepth;
1128 boolean_t groupFlush;
1129 u_int8_t reserved[7];
1130 } STREAM_DETECT, *PTR_STREAM_DETECT;
1131
1132 typedef struct _LD_STREAM_DETECT {
1133 boolean_t writeBack;
1134 boolean_t FPWriteEnabled;
1135 boolean_t membersSSDs;
1136 boolean_t fpCacheBypassCapable;
1137 u_int32_t mruBitMap;
1138 volatile long iosToFware;
1139 volatile long writeBytesOutstanding;
1140 STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED];
1141 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT;
1142
1143 typedef struct _MR_LD_TARGET_SYNC {
1144 u_int8_t targetId;
1145 u_int8_t reserved;
1146 u_int16_t seqNum;
1147 } MR_LD_TARGET_SYNC;
1148
1149 /*
1150 * RAID Map descriptor Types.
1151 * Each element should uniquely idetify one data structure in the RAID map
1152 */
1153 typedef enum _MR_RAID_MAP_DESC_TYPE {
1154 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */
1155 RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */
1156 RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */
1157 RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */
1158 RAID_MAP_DESC_TYPE_COUNT,
1159 } MR_RAID_MAP_DESC_TYPE;
1160
1161 /*
1162 * This table defines the offset, size and num elements of each descriptor
1163 * type in the RAID Map buffer
1164 */
1165 typedef struct _MR_RAID_MAP_DESC_TABLE {
1166 /* Raid map descriptor type */
1167 u_int32_t raidMapDescType;
1168 /* Offset into the RAID map buffer where descriptor data is saved */
1169 u_int32_t raidMapDescOffset;
1170 /* total size of the descriptor buffer */
1171 u_int32_t raidMapDescBufferSize;
1172 /* Number of elements contained in the descriptor buffer */
1173 u_int32_t raidMapDescElements;
1174 } MR_RAID_MAP_DESC_TABLE;
1175
1176 /*
1177 * Dynamic Raid Map Structure.
1178 */
1179 typedef struct _MR_FW_RAID_MAP_DYNAMIC {
1180 u_int32_t raidMapSize;
1181 u_int32_t descTableOffset;
1182 u_int32_t descTableSize;
1183 u_int32_t descTableNumElements;
1184 u_int64_t PCIThresholdBandwidth;
1185 u_int32_t reserved2[3];
1186
1187 u_int8_t fpPdIoTimeoutSec;
1188 u_int8_t reserved3[3];
1189 u_int32_t rmwFPSeqNum;
1190 u_int16_t ldCount;
1191 u_int16_t arCount;
1192 u_int16_t spanCount;
1193 u_int16_t reserved4[3];
1194
1195 /*
1196 * The below structure of pointers is only to be used by the driver.
1197 * This is added in the API to reduce the amount of code changes needed in
1198 * the driver to support dynamic RAID map.
1199 * Firmware should not update these pointers while preparing the raid map
1200 */
1201 union {
1202 struct {
1203 MR_DEV_HANDLE_INFO *devHndlInfo;
1204 u_int16_t *ldTgtIdToLd;
1205 MR_ARRAY_INFO *arMapInfo;
1206 MR_LD_SPAN_MAP *ldSpanMap;
1207 } ptrStruct;
1208 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT];
1209 } RaidMapDescPtrs;
1210
1211 /*
1212 * RAID Map descriptor table defines the layout of data in the RAID Map.
1213 * The size of the descriptor table itself could change.
1214 */
1215
1216 /* Variable Size descriptor Table. */
1217 MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT];
1218 /* Variable Size buffer containing all data */
1219 u_int32_t raidMapDescData[1];
1220
1221 } MR_FW_RAID_MAP_DYNAMIC;
1222
1223 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1224 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1225 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1226 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1227 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1228 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1229 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1230
1231 /* Few NVME flags defines*/
1232 #define MPI2_SGE_FLAGS_SHIFT (0x02)
1233 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1234 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1235 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01)
1236 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1237 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03)
1238
1239 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1240 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1241 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04)
1242 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1243 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C)
1244 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1245
1246 union desc_value {
1247 u_int64_t word;
1248 struct {
1249 u_int32_t low;
1250 u_int32_t high;
1251 } u;
1252 };
1253
1254 /*******************************************************************
1255 * Temporary command
1256 ********************************************************************/
1257 struct mrsas_tmp_dcmd {
1258 bus_dma_tag_t tmp_dcmd_tag;
1259 bus_dmamap_t tmp_dcmd_dmamap;
1260 void *tmp_dcmd_mem;
1261 bus_addr_t tmp_dcmd_phys_addr;
1262 };
1263
1264 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1265 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1266 #define MR_MIN_MAP_SIZE 0x10000
1267
1268 /*******************************************************************
1269 * Register set, included legacy controllers 1068 and 1078,
1270 * structure extended for 1078 registers
1271 *******************************************************************/
1272 #pragma pack(1)
1273 typedef struct _mrsas_register_set {
1274 u_int32_t doorbell; /* 0000h */
1275 u_int32_t fusion_seq_offset; /* 0004h */
1276 u_int32_t fusion_host_diag; /* 0008h */
1277 u_int32_t reserved_01; /* 000Ch */
1278
1279 u_int32_t inbound_msg_0; /* 0010h */
1280 u_int32_t inbound_msg_1; /* 0014h */
1281 u_int32_t outbound_msg_0; /* 0018h */
1282 u_int32_t outbound_msg_1; /* 001Ch */
1283
1284 u_int32_t inbound_doorbell; /* 0020h */
1285 u_int32_t inbound_intr_status; /* 0024h */
1286 u_int32_t inbound_intr_mask; /* 0028h */
1287
1288 u_int32_t outbound_doorbell; /* 002Ch */
1289 u_int32_t outbound_intr_status; /* 0030h */
1290 u_int32_t outbound_intr_mask; /* 0034h */
1291
1292 u_int32_t reserved_1[2]; /* 0038h */
1293
1294 u_int32_t inbound_queue_port; /* 0040h */
1295 u_int32_t outbound_queue_port; /* 0044h */
1296
1297 u_int32_t reserved_2[9]; /* 0048h */
1298 u_int32_t reply_post_host_index;/* 006Ch */
1299 u_int32_t reserved_2_2[12]; /* 0070h */
1300
1301 u_int32_t outbound_doorbell_clear; /* 00A0h */
1302
1303 u_int32_t reserved_3[3]; /* 00A4h */
1304
1305 u_int32_t outbound_scratch_pad; /* 00B0h */
1306 u_int32_t outbound_scratch_pad_2; /* 00B4h */
1307 u_int32_t outbound_scratch_pad_3; /* 00B8h */
1308 u_int32_t outbound_scratch_pad_4; /* 00BCh */
1309
1310 u_int32_t inbound_low_queue_port; /* 00C0h */
1311
1312 u_int32_t inbound_high_queue_port; /* 00C4h */
1313
1314 u_int32_t inbound_single_queue_port; /* 00C8h */
1315 u_int32_t res_6[11]; /* CCh */
1316 u_int32_t host_diag;
1317 u_int32_t seq_offset;
1318 u_int32_t index_registers[807]; /* 00CCh */
1319 } mrsas_reg_set;
1320
1321 #pragma pack()
1322
1323 /*******************************************************************
1324 * Firmware Interface Defines
1325 *******************************************************************
1326 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
1327 * for protocol between the software and firmware. Commands are
1328 * issued using "message frames".
1329 ******************************************************************/
1330 /*
1331 * FW posts its state in upper 4 bits of outbound_msg_0 register
1332 */
1333 #define MFI_STATE_MASK 0xF0000000
1334 #define MFI_STATE_UNDEFINED 0x00000000
1335 #define MFI_STATE_BB_INIT 0x10000000
1336 #define MFI_STATE_FW_INIT 0x40000000
1337 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
1338 #define MFI_STATE_FW_INIT_2 0x70000000
1339 #define MFI_STATE_DEVICE_SCAN 0x80000000
1340 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
1341 #define MFI_STATE_FLUSH_CACHE 0xA0000000
1342 #define MFI_STATE_READY 0xB0000000
1343 #define MFI_STATE_OPERATIONAL 0xC0000000
1344 #define MFI_STATE_FAULT 0xF0000000
1345 #define MFI_RESET_REQUIRED 0x00000001
1346 #define MFI_RESET_ADAPTER 0x00000002
1347 #define MEGAMFI_FRAME_SIZE 64
1348 #define MRSAS_MFI_FRAME_SIZE 1024
1349 #define MRSAS_MFI_SENSE_SIZE 128
1350
1351 /*
1352 * During FW init, clear pending cmds & reset state using inbound_msg_0
1353 *
1354 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to
1355 * READY state; discard queue info MFIMODE : Discard (possible) low MFA
1356 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from
1357 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send
1358 * signal to FW to stop processing
1359 */
1360
1361 #define WRITE_SEQUENCE_OFFSET (0x0000000FC)
1362 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8)
1363 #define DIAG_WRITE_ENABLE (0x00000080)
1364 #define DIAG_RESET_ADAPTER (0x00000004)
1365
1366 #define MFI_ADP_RESET 0x00000040
1367 #define MFI_INIT_ABORT 0x00000001
1368 #define MFI_INIT_READY 0x00000002
1369 #define MFI_INIT_MFIMODE 0x00000004
1370 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
1371 #define MFI_INIT_HOTPLUG 0x00000010
1372 #define MFI_STOP_ADP 0x00000020
1373 #define MFI_RESET_FLAGS MFI_INIT_READY| \
1374 MFI_INIT_MFIMODE| \
1375 MFI_INIT_ABORT
1376
1377 /*
1378 * MFI frame flags
1379 */
1380 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
1381 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
1382 #define MFI_FRAME_SGL32 0x0000
1383 #define MFI_FRAME_SGL64 0x0002
1384 #define MFI_FRAME_SENSE32 0x0000
1385 #define MFI_FRAME_SENSE64 0x0004
1386 #define MFI_FRAME_DIR_NONE 0x0000
1387 #define MFI_FRAME_DIR_WRITE 0x0008
1388 #define MFI_FRAME_DIR_READ 0x0010
1389 #define MFI_FRAME_DIR_BOTH 0x0018
1390 #define MFI_FRAME_IEEE 0x0020
1391
1392 /*
1393 * Definition for cmd_status
1394 */
1395 #define MFI_CMD_STATUS_POLL_MODE 0xFF
1396
1397 /*
1398 * MFI command opcodes
1399 */
1400 #define MFI_CMD_INIT 0x00
1401 #define MFI_CMD_LD_READ 0x01
1402 #define MFI_CMD_LD_WRITE 0x02
1403 #define MFI_CMD_LD_SCSI_IO 0x03
1404 #define MFI_CMD_PD_SCSI_IO 0x04
1405 #define MFI_CMD_DCMD 0x05
1406 #define MFI_CMD_ABORT 0x06
1407 #define MFI_CMD_SMP 0x07
1408 #define MFI_CMD_STP 0x08
1409 #define MFI_CMD_INVALID 0xff
1410
1411 #define MR_DCMD_CTRL_GET_INFO 0x01010000
1412 #define MR_DCMD_LD_GET_LIST 0x03010000
1413 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
1414 #define MR_FLUSH_CTRL_CACHE 0x01
1415 #define MR_FLUSH_DISK_CACHE 0x02
1416
1417 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
1418 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
1419 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
1420
1421 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
1422 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
1423 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
1424 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
1425
1426 #define MR_DCMD_CLUSTER 0x08000000
1427 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
1428 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
1429 #define MR_DCMD_PD_LIST_QUERY 0x02010100
1430
1431 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200
1432 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201
1433 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202
1434 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203
1435 #define MAX_MR_ROW_SIZE 32
1436 #define MR_CPX_DIR_WRITE 1
1437 #define MR_CPX_DIR_READ 0
1438 #define MR_CPX_VERSION 1
1439
1440 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200
1441
1442 #define MR_EVT_CFG_CLEARED 0x0004
1443
1444 #define MR_EVT_LD_STATE_CHANGE 0x0051
1445 #define MR_EVT_PD_INSERTED 0x005b
1446 #define MR_EVT_PD_REMOVED 0x0070
1447 #define MR_EVT_LD_CREATED 0x008a
1448 #define MR_EVT_LD_DELETED 0x008b
1449 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1450 #define MR_EVT_LD_OFFLINE 0x00fc
1451 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1452 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e
1453
1454 /*
1455 * MFI command completion codes
1456 */
1457 enum MFI_STAT {
1458 MFI_STAT_OK = 0x00,
1459 MFI_STAT_INVALID_CMD = 0x01,
1460 MFI_STAT_INVALID_DCMD = 0x02,
1461 MFI_STAT_INVALID_PARAMETER = 0x03,
1462 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1463 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1464 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1465 MFI_STAT_APP_IN_USE = 0x07,
1466 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1467 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1468 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1469 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1470 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1471 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1472 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1473 MFI_STAT_FLASH_BUSY = 0x0f,
1474 MFI_STAT_FLASH_ERROR = 0x10,
1475 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1476 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1477 MFI_STAT_FLASH_NOT_OPEN = 0x13,
1478 MFI_STAT_FLASH_NOT_STARTED = 0x14,
1479 MFI_STAT_FLUSH_FAILED = 0x15,
1480 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1481 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1482 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1483 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1484 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1485 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1486 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1487 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1488 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1489 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1490 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1491 MFI_STAT_MFC_HW_ERROR = 0x21,
1492 MFI_STAT_NO_HW_PRESENT = 0x22,
1493 MFI_STAT_NOT_FOUND = 0x23,
1494 MFI_STAT_NOT_IN_ENCL = 0x24,
1495 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1496 MFI_STAT_PD_TYPE_WRONG = 0x26,
1497 MFI_STAT_PR_DISABLED = 0x27,
1498 MFI_STAT_ROW_INDEX_INVALID = 0x28,
1499 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1500 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1501 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1502 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1503 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1504 MFI_STAT_SCSI_IO_FAILED = 0x2e,
1505 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1506 MFI_STAT_SHUTDOWN_FAILED = 0x30,
1507 MFI_STAT_TIME_NOT_SET = 0x31,
1508 MFI_STAT_WRONG_STATE = 0x32,
1509 MFI_STAT_LD_OFFLINE = 0x33,
1510 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1511 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1512 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1513 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1514 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1515 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1516
1517 MFI_STAT_INVALID_STATUS = 0xFF
1518 };
1519
1520 /*
1521 * Number of mailbox bytes in DCMD message frame
1522 */
1523 #define MFI_MBOX_SIZE 12
1524
1525 enum MR_EVT_CLASS {
1526 MR_EVT_CLASS_DEBUG = -2,
1527 MR_EVT_CLASS_PROGRESS = -1,
1528 MR_EVT_CLASS_INFO = 0,
1529 MR_EVT_CLASS_WARNING = 1,
1530 MR_EVT_CLASS_CRITICAL = 2,
1531 MR_EVT_CLASS_FATAL = 3,
1532 MR_EVT_CLASS_DEAD = 4,
1533
1534 };
1535
1536 enum MR_EVT_LOCALE {
1537 MR_EVT_LOCALE_LD = 0x0001,
1538 MR_EVT_LOCALE_PD = 0x0002,
1539 MR_EVT_LOCALE_ENCL = 0x0004,
1540 MR_EVT_LOCALE_BBU = 0x0008,
1541 MR_EVT_LOCALE_SAS = 0x0010,
1542 MR_EVT_LOCALE_CTRL = 0x0020,
1543 MR_EVT_LOCALE_CONFIG = 0x0040,
1544 MR_EVT_LOCALE_CLUSTER = 0x0080,
1545 MR_EVT_LOCALE_ALL = 0xffff,
1546
1547 };
1548
1549 enum MR_EVT_ARGS {
1550 MR_EVT_ARGS_NONE,
1551 MR_EVT_ARGS_CDB_SENSE,
1552 MR_EVT_ARGS_LD,
1553 MR_EVT_ARGS_LD_COUNT,
1554 MR_EVT_ARGS_LD_LBA,
1555 MR_EVT_ARGS_LD_OWNER,
1556 MR_EVT_ARGS_LD_LBA_PD_LBA,
1557 MR_EVT_ARGS_LD_PROG,
1558 MR_EVT_ARGS_LD_STATE,
1559 MR_EVT_ARGS_LD_STRIP,
1560 MR_EVT_ARGS_PD,
1561 MR_EVT_ARGS_PD_ERR,
1562 MR_EVT_ARGS_PD_LBA,
1563 MR_EVT_ARGS_PD_LBA_LD,
1564 MR_EVT_ARGS_PD_PROG,
1565 MR_EVT_ARGS_PD_STATE,
1566 MR_EVT_ARGS_PCI,
1567 MR_EVT_ARGS_RATE,
1568 MR_EVT_ARGS_STR,
1569 MR_EVT_ARGS_TIME,
1570 MR_EVT_ARGS_ECC,
1571 MR_EVT_ARGS_LD_PROP,
1572 MR_EVT_ARGS_PD_SPARE,
1573 MR_EVT_ARGS_PD_INDEX,
1574 MR_EVT_ARGS_DIAG_PASS,
1575 MR_EVT_ARGS_DIAG_FAIL,
1576 MR_EVT_ARGS_PD_LBA_LBA,
1577 MR_EVT_ARGS_PORT_PHY,
1578 MR_EVT_ARGS_PD_MISSING,
1579 MR_EVT_ARGS_PD_ADDRESS,
1580 MR_EVT_ARGS_BITMAP,
1581 MR_EVT_ARGS_CONNECTOR,
1582 MR_EVT_ARGS_PD_PD,
1583 MR_EVT_ARGS_PD_FRU,
1584 MR_EVT_ARGS_PD_PATHINFO,
1585 MR_EVT_ARGS_PD_POWER_STATE,
1586 MR_EVT_ARGS_GENERIC,
1587 };
1588
1589 /*
1590 * Thunderbolt (and later) Defines
1591 */
1592 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
1593 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
1594 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
1595 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
1596 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
1597 #define MRSAS_LOAD_BALANCE_FLAG 0x1
1598 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1
1599 #define HOST_DIAG_WRITE_ENABLE 0x80
1600 #define HOST_DIAG_RESET_ADAPTER 0x4
1601 #define MRSAS_TBOLT_MAX_RESET_TRIES 3
1602 #define MRSAS_MAX_MFI_CMDS 16
1603 #define MRSAS_MAX_IOCTL_CMDS 3
1604
1605 /*
1606 * Invader Defines
1607 */
1608 #define MPI2_TYPE_CUDA 0x2
1609 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
1610 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
1611 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
1612 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
1613 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
1614 #define MR_RL_WRITE_THROUGH_MODE 0x00
1615 #define MR_RL_WRITE_BACK_MODE 0x01
1616
1617 /*
1618 * T10 PI defines
1619 */
1620 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
1621 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
1622 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9
1623 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB
1624 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18
1625 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20
1626 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60
1627 #define MRSAS_SCSIBLOCKSIZE 512
1628
1629 /*
1630 * Raid context flags
1631 */
1632 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
1633 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
1634 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1635 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1636 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1637 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
1638 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
1639 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
1640 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
1641 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
1642 } MR_RAID_FLAGS_IO_SUB_TYPE;
1643 /*
1644 * Request descriptor types
1645 */
1646 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
1647 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1
1648 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
1649 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
1650 #define MRSAS_FP_CMD_LEN 16
1651 #define MRSAS_FUSION_IN_RESET 0
1652
1653 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
1654 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
1655 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
1656 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
1657
1658 /*
1659 * Define region lock types
1660 */
1661 typedef enum _REGION_TYPE {
1662 REGION_TYPE_UNUSED = 0,
1663 REGION_TYPE_SHARED_READ = 1,
1664 REGION_TYPE_SHARED_WRITE = 2,
1665 REGION_TYPE_EXCLUSIVE = 3,
1666 } REGION_TYPE;
1667
1668 /*
1669 * SCSI-CAM Related Defines
1670 */
1671 #define MRSAS_SCSI_MAX_LUNS 0
1672 #define MRSAS_SCSI_INITIATOR_ID 255
1673 #define MRSAS_SCSI_MAX_CMDS 8
1674 #define MRSAS_SCSI_MAX_CDB_LEN 16
1675 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96
1676 #define MRSAS_INTERNAL_CMDS 32
1677 #define MRSAS_FUSION_INT_CMDS 8
1678
1679 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
1680 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
1681 #define MEGASAS_256K_IO 128
1682 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
1683
1684 /* Request types */
1685 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0
1686 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1
1687 #define MRSAS_REQ_TYPE_PASSTHRU 0x2
1688 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3
1689 #define MRSAS_REQ_TYPE_SCSI_IO 0x4
1690
1691 /* Request states */
1692 #define MRSAS_REQ_STATE_FREE 0
1693 #define MRSAS_REQ_STATE_BUSY 1
1694 #define MRSAS_REQ_STATE_TRAN 2
1695 #define MRSAS_REQ_STATE_COMPLETE 3
1696
1697 typedef enum _MR_SCSI_CMD_TYPE {
1698 READ_WRITE_LDIO = 0,
1699 NON_READ_WRITE_LDIO = 1,
1700 READ_WRITE_SYSPDIO = 2,
1701 NON_READ_WRITE_SYSPDIO = 3,
1702 } MR_SCSI_CMD_TYPE;
1703
1704 enum mrsas_req_flags {
1705 MRSAS_DIR_UNKNOWN = 0x1,
1706 MRSAS_DIR_IN = 0x2,
1707 MRSAS_DIR_OUT = 0x4,
1708 MRSAS_DIR_NONE = 0x8,
1709 };
1710
1711 /*
1712 * Adapter Reset States
1713 */
1714 enum {
1715 MRSAS_HBA_OPERATIONAL = 0,
1716 MRSAS_ADPRESET_SM_INFAULT = 1,
1717 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1718 MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1719 MRSAS_HW_CRITICAL_ERROR = 4,
1720 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1721 };
1722
1723 /*
1724 * MPT Command Structure
1725 */
1726 struct mrsas_mpt_cmd {
1727 MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1728 bus_addr_t io_request_phys_addr;
1729 MPI2_SGE_IO_UNION *chain_frame;
1730 bus_addr_t chain_frame_phys_addr;
1731 u_int32_t sge_count;
1732 u_int8_t *sense;
1733 bus_addr_t sense_phys_addr;
1734 u_int8_t retry_for_fw_reset;
1735 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1736 u_int32_t sync_cmd_idx;
1737 u_int32_t index;
1738 u_int8_t flags;
1739 u_int8_t pd_r1_lb;
1740 u_int8_t load_balance;
1741 bus_size_t length;
1742 u_int32_t error_code;
1743 bus_dmamap_t data_dmamap;
1744 void *data;
1745 union ccb *ccb_ptr;
1746 struct callout cm_callout;
1747 struct mrsas_softc *sc;
1748 boolean_t tmCapable;
1749 u_int16_t r1_alt_dev_handle;
1750 boolean_t cmd_completed;
1751 struct mrsas_mpt_cmd *peer_cmd;
1752 bool callout_owner;
1753 TAILQ_ENTRY(mrsas_mpt_cmd) next;
1754 u_int8_t pdInterface;
1755 };
1756
1757 /*
1758 * MFI Command Structure
1759 */
1760 struct mrsas_mfi_cmd {
1761 union mrsas_frame *frame;
1762 bus_dmamap_t frame_dmamap;
1763 void *frame_mem;
1764 bus_addr_t frame_phys_addr;
1765 u_int8_t *sense;
1766 bus_dmamap_t sense_dmamap;
1767 void *sense_mem;
1768 bus_addr_t sense_phys_addr;
1769 u_int32_t index;
1770 u_int8_t sync_cmd;
1771 u_int8_t cmd_status;
1772 u_int8_t abort_aen;
1773 u_int8_t retry_for_fw_reset;
1774 struct mrsas_softc *sc;
1775 union ccb *ccb_ptr;
1776 union {
1777 struct {
1778 u_int16_t smid;
1779 u_int16_t resvd;
1780 } context;
1781 u_int32_t frame_count;
1782 } cmd_id;
1783 TAILQ_ENTRY(mrsas_mfi_cmd) next;
1784 };
1785
1786 /*
1787 * define constants for device list query options
1788 */
1789 enum MR_PD_QUERY_TYPE {
1790 MR_PD_QUERY_TYPE_ALL = 0,
1791 MR_PD_QUERY_TYPE_STATE = 1,
1792 MR_PD_QUERY_TYPE_POWER_STATE = 2,
1793 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1794 MR_PD_QUERY_TYPE_SPEED = 4,
1795 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1796 };
1797
1798 #define MR_EVT_CFG_CLEARED 0x0004
1799 #define MR_EVT_LD_STATE_CHANGE 0x0051
1800 #define MR_EVT_PD_INSERTED 0x005b
1801 #define MR_EVT_PD_REMOVED 0x0070
1802 #define MR_EVT_LD_CREATED 0x008a
1803 #define MR_EVT_LD_DELETED 0x008b
1804 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1805 #define MR_EVT_LD_OFFLINE 0x00fc
1806 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
1807 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1808
1809 enum MR_PD_STATE {
1810 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1811 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1812 MR_PD_STATE_HOT_SPARE = 0x02,
1813 MR_PD_STATE_OFFLINE = 0x10,
1814 MR_PD_STATE_FAILED = 0x11,
1815 MR_PD_STATE_REBUILD = 0x14,
1816 MR_PD_STATE_ONLINE = 0x18,
1817 MR_PD_STATE_COPYBACK = 0x20,
1818 MR_PD_STATE_SYSTEM = 0x40,
1819 };
1820
1821 /*
1822 * defines the physical drive address structure
1823 */
1824 #pragma pack(1)
1825 struct MR_PD_ADDRESS {
1826 u_int16_t deviceId;
1827 u_int16_t enclDeviceId;
1828
1829 union {
1830 struct {
1831 u_int8_t enclIndex;
1832 u_int8_t slotNumber;
1833 } mrPdAddress;
1834 struct {
1835 u_int8_t enclPosition;
1836 u_int8_t enclConnectorIndex;
1837 } mrEnclAddress;
1838 } u1;
1839 u_int8_t scsiDevType;
1840 union {
1841 u_int8_t connectedPortBitmap;
1842 u_int8_t connectedPortNumbers;
1843 } u2;
1844 u_int64_t sasAddr[2];
1845 };
1846
1847 #pragma pack()
1848
1849 /*
1850 * defines the physical drive list structure
1851 */
1852 #pragma pack(1)
1853 struct MR_PD_LIST {
1854 u_int32_t size;
1855 u_int32_t count;
1856 struct MR_PD_ADDRESS addr[1];
1857 };
1858
1859 #pragma pack()
1860
1861 #pragma pack(1)
1862 struct mrsas_pd_list {
1863 u_int16_t tid;
1864 u_int8_t driveType;
1865 u_int8_t driveState;
1866 };
1867
1868 #pragma pack()
1869
1870 /*
1871 * defines the logical drive reference structure
1872 */
1873 typedef union _MR_LD_REF {
1874 struct {
1875 u_int8_t targetId;
1876 u_int8_t reserved;
1877 u_int16_t seqNum;
1878 } ld_context;
1879 u_int32_t ref;
1880 } MR_LD_REF;
1881
1882 /*
1883 * defines the logical drive list structure
1884 */
1885 #pragma pack(1)
1886 struct MR_LD_LIST {
1887 u_int32_t ldCount;
1888 u_int32_t reserved;
1889 struct {
1890 MR_LD_REF ref;
1891 u_int8_t state;
1892 u_int8_t reserved[3];
1893 u_int64_t size;
1894 } ldList[MAX_LOGICAL_DRIVES_EXT];
1895 };
1896
1897 #pragma pack()
1898
1899 /*
1900 * SAS controller properties
1901 */
1902 #pragma pack(1)
1903 struct mrsas_ctrl_prop {
1904 u_int16_t seq_num;
1905 u_int16_t pred_fail_poll_interval;
1906 u_int16_t intr_throttle_count;
1907 u_int16_t intr_throttle_timeouts;
1908 u_int8_t rebuild_rate;
1909 u_int8_t patrol_read_rate;
1910 u_int8_t bgi_rate;
1911 u_int8_t cc_rate;
1912 u_int8_t recon_rate;
1913 u_int8_t cache_flush_interval;
1914 u_int8_t spinup_drv_count;
1915 u_int8_t spinup_delay;
1916 u_int8_t cluster_enable;
1917 u_int8_t coercion_mode;
1918 u_int8_t alarm_enable;
1919 u_int8_t disable_auto_rebuild;
1920 u_int8_t disable_battery_warn;
1921 u_int8_t ecc_bucket_size;
1922 u_int16_t ecc_bucket_leak_rate;
1923 u_int8_t restore_hotspare_on_insertion;
1924 u_int8_t expose_encl_devices;
1925 u_int8_t maintainPdFailHistory;
1926 u_int8_t disallowHostRequestReordering;
1927 u_int8_t abortCCOnError;
1928 u_int8_t loadBalanceMode;
1929 u_int8_t disableAutoDetectBackplane;
1930 u_int8_t snapVDSpace;
1931 /*
1932 * Add properties that can be controlled by a bit in the following
1933 * structure.
1934 */
1935 struct {
1936 #if _BYTE_ORDER == _LITTLE_ENDIAN
1937 u_int32_t copyBackDisabled:1;
1938 u_int32_t SMARTerEnabled:1;
1939 u_int32_t prCorrectUnconfiguredAreas:1;
1940 u_int32_t useFdeOnly:1;
1941 u_int32_t disableNCQ:1;
1942 u_int32_t SSDSMARTerEnabled:1;
1943 u_int32_t SSDPatrolReadEnabled:1;
1944 u_int32_t enableSpinDownUnconfigured:1;
1945 u_int32_t autoEnhancedImport:1;
1946 u_int32_t enableSecretKeyControl:1;
1947 u_int32_t disableOnlineCtrlReset:1;
1948 u_int32_t allowBootWithPinnedCache:1;
1949 u_int32_t disableSpinDownHS:1;
1950 u_int32_t enableJBOD:1;
1951 u_int32_t disableCacheBypass:1;
1952 u_int32_t useDiskActivityForLocate:1;
1953 u_int32_t enablePI:1;
1954 u_int32_t preventPIImport:1;
1955 u_int32_t useGlobalSparesForEmergency:1;
1956 u_int32_t useUnconfGoodForEmergency:1;
1957 u_int32_t useEmergencySparesforSMARTer:1;
1958 u_int32_t forceSGPIOForQuadOnly:1;
1959 u_int32_t enableConfigAutoBalance:1;
1960 u_int32_t enableVirtualCache:1;
1961 u_int32_t enableAutoLockRecovery:1;
1962 u_int32_t disableImmediateIO:1;
1963 u_int32_t disableT10RebuildAssist:1;
1964 u_int32_t ignore64ldRestriction:1;
1965 u_int32_t enableSwZone:1;
1966 u_int32_t limitMaxRateSATA3G:1;
1967 u_int32_t reserved:2;
1968 #else
1969 u_int32_t reserved:2;
1970 u_int32_t limitMaxRateSATA3G:1;
1971 u_int32_t enableSwZone:1;
1972 u_int32_t ignore64ldRestriction:1;
1973 u_int32_t disableT10RebuildAssist:1;
1974 u_int32_t disableImmediateIO:1;
1975 u_int32_t enableAutoLockRecovery:1;
1976 u_int32_t enableVirtualCache:1;
1977 u_int32_t enableConfigAutoBalance:1;
1978 u_int32_t forceSGPIOForQuadOnly:1;
1979 u_int32_t useEmergencySparesforSMARTer:1;
1980 u_int32_t useUnconfGoodForEmergency:1;
1981 u_int32_t useGlobalSparesForEmergency:1;
1982 u_int32_t preventPIImport:1;
1983 u_int32_t enablePI:1;
1984 u_int32_t useDiskActivityForLocate:1;
1985 u_int32_t disableCacheBypass:1;
1986 u_int32_t enableJBOD:1;
1987 u_int32_t disableSpinDownHS:1;
1988 u_int32_t allowBootWithPinnedCache:1;
1989 u_int32_t disableOnlineCtrlReset:1;
1990 u_int32_t enableSecretKeyControl:1;
1991 u_int32_t autoEnhancedImport:1;
1992 u_int32_t enableSpinDownUnconfigured:1;
1993 u_int32_t SSDPatrolReadEnabled:1;
1994 u_int32_t SSDSMARTerEnabled:1;
1995 u_int32_t disableNCQ:1;
1996 u_int32_t useFdeOnly:1;
1997 u_int32_t prCorrectUnconfiguredAreas:1;
1998 u_int32_t SMARTerEnabled:1;
1999 u_int32_t copyBackDisabled:1;
2000 #endif
2001 } OnOffProperties;
2002 u_int8_t autoSnapVDSpace;
2003 u_int8_t viewSpace;
2004 u_int16_t spinDownTime;
2005 u_int8_t reserved[24];
2006
2007 };
2008
2009 #pragma pack()
2010
2011 /*
2012 * SAS controller information
2013 */
2014 struct mrsas_ctrl_info {
2015 /*
2016 * PCI device information
2017 */
2018 struct {
2019 u_int16_t vendor_id;
2020 u_int16_t device_id;
2021 u_int16_t sub_vendor_id;
2022 u_int16_t sub_device_id;
2023 u_int8_t reserved[24];
2024 } __packed pci;
2025 /*
2026 * Host interface information
2027 */
2028 struct {
2029 u_int8_t PCIX:1;
2030 u_int8_t PCIE:1;
2031 u_int8_t iSCSI:1;
2032 u_int8_t SAS_3G:1;
2033 u_int8_t reserved_0:4;
2034 u_int8_t reserved_1[6];
2035 u_int8_t port_count;
2036 u_int64_t port_addr[8];
2037 } __packed host_interface;
2038 /*
2039 * Device (backend) interface information
2040 */
2041 struct {
2042 u_int8_t SPI:1;
2043 u_int8_t SAS_3G:1;
2044 u_int8_t SATA_1_5G:1;
2045 u_int8_t SATA_3G:1;
2046 u_int8_t reserved_0:4;
2047 u_int8_t reserved_1[6];
2048 u_int8_t port_count;
2049 u_int64_t port_addr[8];
2050 } __packed device_interface;
2051
2052 u_int32_t image_check_word;
2053 u_int32_t image_component_count;
2054
2055 struct {
2056 char name[8];
2057 char version[32];
2058 char build_date[16];
2059 char built_time[16];
2060 } __packed image_component[8];
2061
2062 u_int32_t pending_image_component_count;
2063
2064 struct {
2065 char name[8];
2066 char version[32];
2067 char build_date[16];
2068 char build_time[16];
2069 } __packed pending_image_component[8];
2070
2071 u_int8_t max_arms;
2072 u_int8_t max_spans;
2073 u_int8_t max_arrays;
2074 u_int8_t max_lds;
2075 char product_name[80];
2076 char serial_no[32];
2077
2078 /*
2079 * Other physical/controller/operation information. Indicates the
2080 * presence of the hardware
2081 */
2082 struct {
2083 u_int32_t bbu:1;
2084 u_int32_t alarm:1;
2085 u_int32_t nvram:1;
2086 u_int32_t uart:1;
2087 u_int32_t reserved:28;
2088 } __packed hw_present;
2089
2090 u_int32_t current_fw_time;
2091
2092 /*
2093 * Maximum data transfer sizes
2094 */
2095 u_int16_t max_concurrent_cmds;
2096 u_int16_t max_sge_count;
2097 u_int32_t max_request_size;
2098
2099 /*
2100 * Logical and physical device counts
2101 */
2102 u_int16_t ld_present_count;
2103 u_int16_t ld_degraded_count;
2104 u_int16_t ld_offline_count;
2105
2106 u_int16_t pd_present_count;
2107 u_int16_t pd_disk_present_count;
2108 u_int16_t pd_disk_pred_failure_count;
2109 u_int16_t pd_disk_failed_count;
2110
2111 /*
2112 * Memory size information
2113 */
2114 u_int16_t nvram_size;
2115 u_int16_t memory_size;
2116 u_int16_t flash_size;
2117
2118 /*
2119 * Error counters
2120 */
2121 u_int16_t mem_correctable_error_count;
2122 u_int16_t mem_uncorrectable_error_count;
2123
2124 /*
2125 * Cluster information
2126 */
2127 u_int8_t cluster_permitted;
2128 u_int8_t cluster_active;
2129
2130 /*
2131 * Additional max data transfer sizes
2132 */
2133 u_int16_t max_strips_per_io;
2134
2135 /*
2136 * Controller capabilities structures
2137 */
2138 struct {
2139 u_int32_t raid_level_0:1;
2140 u_int32_t raid_level_1:1;
2141 u_int32_t raid_level_5:1;
2142 u_int32_t raid_level_1E:1;
2143 u_int32_t raid_level_6:1;
2144 u_int32_t reserved:27;
2145 } __packed raid_levels;
2146
2147 struct {
2148 u_int32_t rbld_rate:1;
2149 u_int32_t cc_rate:1;
2150 u_int32_t bgi_rate:1;
2151 u_int32_t recon_rate:1;
2152 u_int32_t patrol_rate:1;
2153 u_int32_t alarm_control:1;
2154 u_int32_t cluster_supported:1;
2155 u_int32_t bbu:1;
2156 u_int32_t spanning_allowed:1;
2157 u_int32_t dedicated_hotspares:1;
2158 u_int32_t revertible_hotspares:1;
2159 u_int32_t foreign_config_import:1;
2160 u_int32_t self_diagnostic:1;
2161 u_int32_t mixed_redundancy_arr:1;
2162 u_int32_t global_hot_spares:1;
2163 u_int32_t reserved:17;
2164 } __packed adapter_operations;
2165
2166 struct {
2167 u_int32_t read_policy:1;
2168 u_int32_t write_policy:1;
2169 u_int32_t io_policy:1;
2170 u_int32_t access_policy:1;
2171 u_int32_t disk_cache_policy:1;
2172 u_int32_t reserved:27;
2173 } __packed ld_operations;
2174
2175 struct {
2176 u_int8_t min;
2177 u_int8_t max;
2178 u_int8_t reserved[2];
2179 } __packed stripe_sz_ops;
2180
2181 struct {
2182 u_int32_t force_online:1;
2183 u_int32_t force_offline:1;
2184 u_int32_t force_rebuild:1;
2185 u_int32_t reserved:29;
2186 } __packed pd_operations;
2187
2188 struct {
2189 u_int32_t ctrl_supports_sas:1;
2190 u_int32_t ctrl_supports_sata:1;
2191 u_int32_t allow_mix_in_encl:1;
2192 u_int32_t allow_mix_in_ld:1;
2193 u_int32_t allow_sata_in_cluster:1;
2194 u_int32_t reserved:27;
2195 } __packed pd_mix_support;
2196
2197 /*
2198 * Define ECC single-bit-error bucket information
2199 */
2200 u_int8_t ecc_bucket_count;
2201 u_int8_t reserved_2[11];
2202
2203 /*
2204 * Include the controller properties (changeable items)
2205 */
2206 struct mrsas_ctrl_prop properties;
2207
2208 /*
2209 * Define FW pkg version (set in envt v'bles on OEM basis)
2210 */
2211 char package_version[0x60];
2212
2213 u_int64_t deviceInterfacePortAddr2[8];
2214 u_int8_t reserved3[128];
2215
2216 struct {
2217 u_int16_t minPdRaidLevel_0:4;
2218 u_int16_t maxPdRaidLevel_0:12;
2219
2220 u_int16_t minPdRaidLevel_1:4;
2221 u_int16_t maxPdRaidLevel_1:12;
2222
2223 u_int16_t minPdRaidLevel_5:4;
2224 u_int16_t maxPdRaidLevel_5:12;
2225
2226 u_int16_t minPdRaidLevel_1E:4;
2227 u_int16_t maxPdRaidLevel_1E:12;
2228
2229 u_int16_t minPdRaidLevel_6:4;
2230 u_int16_t maxPdRaidLevel_6:12;
2231
2232 u_int16_t minPdRaidLevel_10:4;
2233 u_int16_t maxPdRaidLevel_10:12;
2234
2235 u_int16_t minPdRaidLevel_50:4;
2236 u_int16_t maxPdRaidLevel_50:12;
2237
2238 u_int16_t minPdRaidLevel_60:4;
2239 u_int16_t maxPdRaidLevel_60:12;
2240
2241 u_int16_t minPdRaidLevel_1E_RLQ0:4;
2242 u_int16_t maxPdRaidLevel_1E_RLQ0:12;
2243
2244 u_int16_t minPdRaidLevel_1E0_RLQ0:4;
2245 u_int16_t maxPdRaidLevel_1E0_RLQ0:12;
2246
2247 u_int16_t reserved[6];
2248 } pdsForRaidLevels;
2249
2250 u_int16_t maxPds; /* 0x780 */
2251 u_int16_t maxDedHSPs; /* 0x782 */
2252 u_int16_t maxGlobalHSPs; /* 0x784 */
2253 u_int16_t ddfSize; /* 0x786 */
2254 u_int8_t maxLdsPerArray; /* 0x788 */
2255 u_int8_t partitionsInDDF; /* 0x789 */
2256 u_int8_t lockKeyBinding; /* 0x78a */
2257 u_int8_t maxPITsPerLd; /* 0x78b */
2258 u_int8_t maxViewsPerLd; /* 0x78c */
2259 u_int8_t maxTargetId; /* 0x78d */
2260 u_int16_t maxBvlVdSize; /* 0x78e */
2261
2262 u_int16_t maxConfigurableSSCSize; /* 0x790 */
2263 u_int16_t currentSSCsize; /* 0x792 */
2264
2265 char expanderFwVersion[12]; /* 0x794 */
2266
2267 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
2268
2269 u_int16_t cacheMemorySize; /* 0x7A2 */
2270
2271 struct { /* 0x7A4 */
2272 #if _BYTE_ORDER == _LITTLE_ENDIAN
2273 u_int32_t supportPIcontroller:1;
2274 u_int32_t supportLdPIType1:1;
2275 u_int32_t supportLdPIType2:1;
2276 u_int32_t supportLdPIType3:1;
2277 u_int32_t supportLdBBMInfo:1;
2278 u_int32_t supportShieldState:1;
2279 u_int32_t blockSSDWriteCacheChange:1;
2280 u_int32_t supportSuspendResumeBGops:1;
2281 u_int32_t supportEmergencySpares:1;
2282 u_int32_t supportSetLinkSpeed:1;
2283 u_int32_t supportBootTimePFKChange:1;
2284 u_int32_t supportJBOD:1;
2285 u_int32_t disableOnlinePFKChange:1;
2286 u_int32_t supportPerfTuning:1;
2287 u_int32_t supportSSDPatrolRead:1;
2288 u_int32_t realTimeScheduler:1;
2289
2290 u_int32_t supportResetNow:1;
2291 u_int32_t supportEmulatedDrives:1;
2292 u_int32_t headlessMode:1;
2293 u_int32_t dedicatedHotSparesLimited:1;
2294
2295 u_int32_t supportUnevenSpans:1;
2296 u_int32_t reserved:11;
2297 #else
2298 u_int32_t reserved:11;
2299 u_int32_t supportUnevenSpans:1;
2300 u_int32_t dedicatedHotSparesLimited:1;
2301 u_int32_t headlessMode:1;
2302 u_int32_t supportEmulatedDrives:1;
2303 u_int32_t supportResetNow:1;
2304 u_int32_t realTimeScheduler:1;
2305 u_int32_t supportSSDPatrolRead:1;
2306 u_int32_t supportPerfTuning:1;
2307 u_int32_t disableOnlinePFKChange:1;
2308 u_int32_t supportJBOD:1;
2309 u_int32_t supportBootTimePFKChange:1;
2310 u_int32_t supportSetLinkSpeed:1;
2311 u_int32_t supportEmergencySpares:1;
2312 u_int32_t supportSuspendResumeBGops:1;
2313 u_int32_t blockSSDWriteCacheChange:1;
2314 u_int32_t supportShieldState:1;
2315 u_int32_t supportLdBBMInfo:1;
2316 u_int32_t supportLdPIType3:1;
2317 u_int32_t supportLdPIType2:1;
2318 u_int32_t supportLdPIType1:1;
2319 u_int32_t supportPIcontroller:1;
2320 #endif
2321 } adapterOperations2;
2322
2323 u_int8_t driverVersion[32]; /* 0x7A8 */
2324 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */
2325 u_int8_t temperatureROC; /* 0x7C9 */
2326 u_int8_t temperatureCtrl; /* 0x7CA */
2327 u_int8_t reserved4; /* 0x7CB */
2328 u_int16_t maxConfigurablePds; /* 0x7CC */
2329
2330 u_int8_t reserved5[2]; /* 0x7CD reserved */
2331
2332 struct {
2333 #if _BYTE_ORDER == _LITTLE_ENDIAN
2334 u_int32_t peerIsPresent:1;
2335 u_int32_t peerIsIncompatible:1;
2336
2337 u_int32_t hwIncompatible:1;
2338 u_int32_t fwVersionMismatch:1;
2339 u_int32_t ctrlPropIncompatible:1;
2340 u_int32_t premiumFeatureMismatch:1;
2341 u_int32_t reserved:26;
2342 #else
2343 u_int32_t reserved:26;
2344 u_int32_t premiumFeatureMismatch:1;
2345 u_int32_t ctrlPropIncompatible:1;
2346 u_int32_t fwVersionMismatch:1;
2347 u_int32_t hwIncompatible:1;
2348 u_int32_t peerIsIncompatible:1;
2349 u_int32_t peerIsPresent:1;
2350 #endif
2351 } cluster;
2352
2353 char clusterId[16]; /* 0x7D4 */
2354
2355 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */
2356
2357 struct { /* 0x7E8 */
2358 #if _BYTE_ORDER == _LITTLE_ENDIAN
2359 u_int32_t supportPersonalityChange:2;
2360 u_int32_t supportThermalPollInterval:1;
2361 u_int32_t supportDisableImmediateIO:1;
2362 u_int32_t supportT10RebuildAssist:1;
2363 u_int32_t supportMaxExtLDs:1;
2364 u_int32_t supportCrashDump:1;
2365 u_int32_t supportSwZone:1;
2366 u_int32_t supportDebugQueue:1;
2367 u_int32_t supportNVCacheErase:1;
2368 u_int32_t supportForceTo512e:1;
2369 u_int32_t supportHOQRebuild:1;
2370 u_int32_t supportAllowedOpsforDrvRemoval:1;
2371 u_int32_t supportDrvActivityLEDSetting:1;
2372 u_int32_t supportNVDRAM:1;
2373 u_int32_t supportForceFlash:1;
2374 u_int32_t supportDisableSESMonitoring:1;
2375 u_int32_t supportCacheBypassModes:1;
2376 u_int32_t supportSecurityonJBOD:1;
2377 u_int32_t discardCacheDuringLDDelete:1;
2378 u_int32_t supportTTYLogCompression:1;
2379 u_int32_t supportCPLDUpdate:1;
2380 u_int32_t supportDiskCacheSettingForSysPDs:1;
2381 u_int32_t supportExtendedSSCSize:1;
2382 u_int32_t useSeqNumJbodFP:1;
2383 u_int32_t reserved:7;
2384 #else
2385 u_int32_t reserved:7;
2386 u_int32_t useSeqNumJbodFP:1;
2387 u_int32_t supportExtendedSSCSize:1;
2388 u_int32_t supportDiskCacheSettingForSysPDs:1;
2389 u_int32_t supportCPLDUpdate:1;
2390 u_int32_t supportTTYLogCompression:1;
2391 u_int32_t discardCacheDuringLDDelete:1;
2392 u_int32_t supportSecurityonJBOD:1;
2393 u_int32_t supportCacheBypassModes:1;
2394 u_int32_t supportDisableSESMonitoring:1;
2395 u_int32_t supportForceFlash:1;
2396 u_int32_t supportNVDRAM:1;
2397 u_int32_t supportDrvActivityLEDSetting:1;
2398 u_int32_t supportAllowedOpsforDrvRemoval:1;
2399 u_int32_t supportHOQRebuild:1;
2400 u_int32_t supportForceTo512e:1;
2401 u_int32_t supportNVCacheErase:1;
2402 u_int32_t supportDebugQueue:1;
2403 u_int32_t supportSwZone:1;
2404 u_int32_t supportCrashDump:1;
2405 u_int32_t supportMaxExtLDs:1;
2406 u_int32_t supportT10RebuildAssist:1;
2407 u_int32_t supportDisableImmediateIO:1;
2408 u_int32_t supportThermalPollInterval:1;
2409 u_int32_t supportPersonalityChange:2;
2410 #endif
2411 } adapterOperations3;
2412
2413 u_int8_t pad_cpld[16];
2414
2415 struct {
2416 #if _BYTE_ORDER == _LITTLE_ENDIAN
2417 u_int16_t ctrlInfoExtSupported:1;
2418 u_int16_t supportIbuttonLess:1;
2419 u_int16_t supportedEncAlgo:1;
2420 u_int16_t supportEncryptedMfc:1;
2421 u_int16_t imageUploadSupported:1;
2422 u_int16_t supportSESCtrlInMultipathCfg:1;
2423 u_int16_t supportPdMapTargetId:1;
2424 u_int16_t FWSwapsBBUVPDInfo:1;
2425 u_int16_t reserved:8;
2426 #else
2427 u_int16_t reserved:8;
2428 u_int16_t FWSwapsBBUVPDInfo:1;
2429 u_int16_t supportPdMapTargetId:1;
2430 u_int16_t supportSESCtrlInMultipathCfg:1;
2431 u_int16_t imageUploadSupported:1;
2432 u_int16_t supportEncryptedMfc:1;
2433 u_int16_t supportedEncAlgo:1;
2434 u_int16_t supportIbuttonLess:1;
2435 u_int16_t ctrlInfoExtSupported:1;
2436 #endif
2437 } adapterOperations4;
2438
2439 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */
2440 } __packed;
2441
2442 /*
2443 * When SCSI mid-layer calls driver's reset routine, driver waits for
2444 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
2445 * that the driver cannot _actually_ abort or reset pending commands. While
2446 * it is waiting for the commands to complete, it prints a diagnostic message
2447 * every MRSAS_RESET_NOTICE_INTERVAL seconds
2448 */
2449 #define MRSAS_RESET_WAIT_TIME 180
2450 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180
2451 #define MRSAS_RESET_NOTICE_INTERVAL 5
2452 #define MRSAS_IOCTL_CMD 0
2453 #define MRSAS_DEFAULT_CMD_TIMEOUT 90
2454 #define MRSAS_THROTTLE_QUEUE_DEPTH 16
2455
2456 /*
2457 * MSI-x regsiters offset defines
2458 */
2459 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
2460 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
2461 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F)
2462 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000)
2463 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
2464 #define MR_MAX_MSIX_REG_ARRAY 16
2465
2466 /*
2467 * SYNC CACHE offset define
2468 */
2469 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
2470
2471 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
2472
2473 /*
2474 * FW reports the maximum of number of commands that it can accept (maximum
2475 * commands that can be outstanding) at any time. The driver must report a
2476 * lower number to the mid layer because it can issue a few internal commands
2477 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
2478 * is shown below
2479 */
2480 #define MRSAS_INT_CMDS 32
2481 #define MRSAS_SKINNY_INT_CMDS 5
2482 #define MRSAS_MAX_MSIX_QUEUES 128
2483
2484 /*
2485 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs
2486 * based on the size of bus_addr_t
2487 */
2488 #define IS_DMA64 (sizeof(bus_addr_t) == 8)
2489
2490 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
2491 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
2492 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
2493 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
2494
2495 #define MFI_OB_INTR_STATUS_MASK 0x00000002
2496 #define MFI_POLL_TIMEOUT_SECS 60
2497
2498 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
2499 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
2500 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001
2501 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
2502 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
2503 #define MFI_1068_PCSR_OFFSET 0x84
2504 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
2505 #define MFI_1068_FW_READY 0xDDDD0000
2506
2507 typedef union _MFI_CAPABILITIES {
2508 struct {
2509 #if _BYTE_ORDER == _LITTLE_ENDIAN
2510 u_int32_t support_fp_remote_lun:1;
2511 u_int32_t support_additional_msix:1;
2512 u_int32_t support_fastpath_wb:1;
2513 u_int32_t support_max_255lds:1;
2514 u_int32_t support_ndrive_r1_lb:1;
2515 u_int32_t support_core_affinity:1;
2516 u_int32_t security_protocol_cmds_fw:1;
2517 u_int32_t support_ext_queue_depth:1;
2518 u_int32_t support_ext_io_size:1;
2519 u_int32_t reserved:23;
2520 #else
2521 u_int32_t reserved:23;
2522 u_int32_t support_ext_io_size:1;
2523 u_int32_t support_ext_queue_depth:1;
2524 u_int32_t security_protocol_cmds_fw:1;
2525 u_int32_t support_core_affinity:1;
2526 u_int32_t support_ndrive_r1_lb:1;
2527 u_int32_t support_max_255lds:1;
2528 u_int32_t support_fastpath_wb:1;
2529 u_int32_t support_additional_msix:1;
2530 u_int32_t support_fp_remote_lun:1;
2531 #endif
2532 } mfi_capabilities;
2533 u_int32_t reg;
2534 } MFI_CAPABILITIES;
2535
2536 #pragma pack(1)
2537 struct mrsas_sge32 {
2538 u_int32_t phys_addr;
2539 u_int32_t length;
2540 };
2541
2542 #pragma pack()
2543
2544 #pragma pack(1)
2545 struct mrsas_sge64 {
2546 u_int64_t phys_addr;
2547 u_int32_t length;
2548 };
2549
2550 #pragma pack()
2551
2552 #pragma pack()
2553 union mrsas_sgl {
2554 struct mrsas_sge32 sge32[1];
2555 struct mrsas_sge64 sge64[1];
2556 };
2557
2558 #pragma pack()
2559
2560 #pragma pack(1)
2561 struct mrsas_header {
2562 u_int8_t cmd; /* 00e */
2563 u_int8_t sense_len; /* 01h */
2564 u_int8_t cmd_status; /* 02h */
2565 u_int8_t scsi_status; /* 03h */
2566
2567 u_int8_t target_id; /* 04h */
2568 u_int8_t lun; /* 05h */
2569 u_int8_t cdb_len; /* 06h */
2570 u_int8_t sge_count; /* 07h */
2571
2572 u_int32_t context; /* 08h */
2573 u_int32_t pad_0; /* 0Ch */
2574
2575 u_int16_t flags; /* 10h */
2576 u_int16_t timeout; /* 12h */
2577 u_int32_t data_xferlen; /* 14h */
2578 };
2579
2580 #pragma pack()
2581
2582 #pragma pack(1)
2583 struct mrsas_init_frame {
2584 u_int8_t cmd; /* 00h */
2585 u_int8_t reserved_0; /* 01h */
2586 u_int8_t cmd_status; /* 02h */
2587
2588 u_int8_t reserved_1; /* 03h */
2589 MFI_CAPABILITIES driver_operations; /* 04h */
2590 u_int32_t context; /* 08h */
2591 u_int32_t pad_0; /* 0Ch */
2592
2593 u_int16_t flags; /* 10h */
2594 u_int16_t reserved_3; /* 12h */
2595 u_int32_t data_xfer_len; /* 14h */
2596
2597 u_int32_t queue_info_new_phys_addr_lo; /* 18h */
2598 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */
2599 u_int32_t queue_info_old_phys_addr_lo; /* 20h */
2600 u_int32_t queue_info_old_phys_addr_hi; /* 24h */
2601 u_int32_t driver_ver_lo; /* 28h */
2602 u_int32_t driver_ver_hi; /* 2Ch */
2603 u_int32_t reserved_4[4]; /* 30h */
2604 };
2605
2606 #pragma pack()
2607
2608 #pragma pack(1)
2609 struct mrsas_io_frame {
2610 u_int8_t cmd; /* 00h */
2611 u_int8_t sense_len; /* 01h */
2612 u_int8_t cmd_status; /* 02h */
2613 u_int8_t scsi_status; /* 03h */
2614
2615 u_int8_t target_id; /* 04h */
2616 u_int8_t access_byte; /* 05h */
2617 u_int8_t reserved_0; /* 06h */
2618 u_int8_t sge_count; /* 07h */
2619
2620 u_int32_t context; /* 08h */
2621 u_int32_t pad_0; /* 0Ch */
2622
2623 u_int16_t flags; /* 10h */
2624 u_int16_t timeout; /* 12h */
2625 u_int32_t lba_count; /* 14h */
2626
2627 u_int32_t sense_buf_phys_addr_lo; /* 18h */
2628 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */
2629
2630 u_int32_t start_lba_lo; /* 20h */
2631 u_int32_t start_lba_hi; /* 24h */
2632
2633 union mrsas_sgl sgl; /* 28h */
2634 };
2635
2636 #pragma pack()
2637
2638 #pragma pack(1)
2639 struct mrsas_pthru_frame {
2640 u_int8_t cmd; /* 00h */
2641 u_int8_t sense_len; /* 01h */
2642 u_int8_t cmd_status; /* 02h */
2643 u_int8_t scsi_status; /* 03h */
2644
2645 u_int8_t target_id; /* 04h */
2646 u_int8_t lun; /* 05h */
2647 u_int8_t cdb_len; /* 06h */
2648 u_int8_t sge_count; /* 07h */
2649
2650 u_int32_t context; /* 08h */
2651 u_int32_t pad_0; /* 0Ch */
2652
2653 u_int16_t flags; /* 10h */
2654 u_int16_t timeout; /* 12h */
2655 u_int32_t data_xfer_len; /* 14h */
2656
2657 u_int32_t sense_buf_phys_addr_lo; /* 18h */
2658 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */
2659
2660 u_int8_t cdb[16]; /* 20h */
2661 union mrsas_sgl sgl; /* 30h */
2662 };
2663
2664 #pragma pack()
2665
2666 #pragma pack(1)
2667 struct mrsas_dcmd_frame {
2668 u_int8_t cmd; /* 00h */
2669 u_int8_t reserved_0; /* 01h */
2670 u_int8_t cmd_status; /* 02h */
2671 u_int8_t reserved_1[4]; /* 03h */
2672 u_int8_t sge_count; /* 07h */
2673
2674 u_int32_t context; /* 08h */
2675 u_int32_t pad_0; /* 0Ch */
2676
2677 u_int16_t flags; /* 10h */
2678 u_int16_t timeout; /* 12h */
2679
2680 u_int32_t data_xfer_len; /* 14h */
2681 u_int32_t opcode; /* 18h */
2682
2683 union { /* 1Ch */
2684 u_int8_t b[12];
2685 u_int16_t s[6];
2686 u_int32_t w[3];
2687 } mbox;
2688
2689 union mrsas_sgl sgl; /* 28h */
2690 };
2691
2692 #pragma pack()
2693
2694 #pragma pack(1)
2695 struct mrsas_abort_frame {
2696 u_int8_t cmd; /* 00h */
2697 u_int8_t reserved_0; /* 01h */
2698 u_int8_t cmd_status; /* 02h */
2699
2700 u_int8_t reserved_1; /* 03h */
2701 MFI_CAPABILITIES driver_operations; /* 04h */
2702 u_int32_t context; /* 08h */
2703 u_int32_t pad_0; /* 0Ch */
2704
2705 u_int16_t flags; /* 10h */
2706 u_int16_t reserved_3; /* 12h */
2707 u_int32_t reserved_4; /* 14h */
2708
2709 u_int32_t abort_context; /* 18h */
2710 u_int32_t pad_1; /* 1Ch */
2711
2712 u_int32_t abort_mfi_phys_addr_lo; /* 20h */
2713 u_int32_t abort_mfi_phys_addr_hi; /* 24h */
2714
2715 u_int32_t reserved_5[6]; /* 28h */
2716 };
2717
2718 #pragma pack()
2719
2720 #pragma pack(1)
2721 struct mrsas_smp_frame {
2722 u_int8_t cmd; /* 00h */
2723 u_int8_t reserved_1; /* 01h */
2724 u_int8_t cmd_status; /* 02h */
2725 u_int8_t connection_status; /* 03h */
2726
2727 u_int8_t reserved_2[3]; /* 04h */
2728 u_int8_t sge_count; /* 07h */
2729
2730 u_int32_t context; /* 08h */
2731 u_int32_t pad_0; /* 0Ch */
2732
2733 u_int16_t flags; /* 10h */
2734 u_int16_t timeout; /* 12h */
2735
2736 u_int32_t data_xfer_len; /* 14h */
2737 u_int64_t sas_addr; /* 18h */
2738
2739 union {
2740 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */
2741 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */
2742 } sgl;
2743 };
2744
2745 #pragma pack()
2746
2747 #pragma pack(1)
2748 struct mrsas_stp_frame {
2749 u_int8_t cmd; /* 00h */
2750 u_int8_t reserved_1; /* 01h */
2751 u_int8_t cmd_status; /* 02h */
2752 u_int8_t reserved_2; /* 03h */
2753
2754 u_int8_t target_id; /* 04h */
2755 u_int8_t reserved_3[2]; /* 05h */
2756 u_int8_t sge_count; /* 07h */
2757
2758 u_int32_t context; /* 08h */
2759 u_int32_t pad_0; /* 0Ch */
2760
2761 u_int16_t flags; /* 10h */
2762 u_int16_t timeout; /* 12h */
2763
2764 u_int32_t data_xfer_len; /* 14h */
2765
2766 u_int16_t fis[10]; /* 18h */
2767 u_int32_t stp_flags;
2768
2769 union {
2770 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */
2771 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */
2772 } sgl;
2773 };
2774
2775 #pragma pack()
2776
2777 union mrsas_frame {
2778 struct mrsas_header hdr;
2779 struct mrsas_init_frame init;
2780 struct mrsas_io_frame io;
2781 struct mrsas_pthru_frame pthru;
2782 struct mrsas_dcmd_frame dcmd;
2783 struct mrsas_abort_frame abort;
2784 struct mrsas_smp_frame smp;
2785 struct mrsas_stp_frame stp;
2786 u_int8_t raw_bytes[64];
2787 };
2788
2789 #pragma pack(1)
2790 union mrsas_evt_class_locale {
2791 struct {
2792 #if _BYTE_ORDER == _LITTLE_ENDIAN
2793 u_int16_t locale;
2794 u_int8_t reserved;
2795 int8_t class;
2796 #else
2797 int8_t class;
2798 u_int8_t reserved;
2799 u_int16_t locale;
2800 #endif
2801 } __packed members;
2802
2803 u_int32_t word;
2804
2805 } __packed;
2806
2807 #pragma pack()
2808
2809 #pragma pack(1)
2810 struct mrsas_evt_log_info {
2811 u_int32_t newest_seq_num;
2812 u_int32_t oldest_seq_num;
2813 u_int32_t clear_seq_num;
2814 u_int32_t shutdown_seq_num;
2815 u_int32_t boot_seq_num;
2816
2817 } __packed;
2818
2819 #pragma pack()
2820
2821 struct mrsas_progress {
2822 u_int16_t progress;
2823 u_int16_t elapsed_seconds;
2824
2825 } __packed;
2826
2827 struct mrsas_evtarg_ld {
2828 u_int16_t target_id;
2829 u_int8_t ld_index;
2830 u_int8_t reserved;
2831
2832 } __packed;
2833
2834 struct mrsas_evtarg_pd {
2835 u_int16_t device_id;
2836 u_int8_t encl_index;
2837 u_int8_t slot_number;
2838
2839 } __packed;
2840
2841 struct mrsas_evt_detail {
2842 u_int32_t seq_num;
2843 u_int32_t time_stamp;
2844 u_int32_t code;
2845 union mrsas_evt_class_locale cl;
2846 u_int8_t arg_type;
2847 u_int8_t reserved1[15];
2848
2849 union {
2850 struct {
2851 struct mrsas_evtarg_pd pd;
2852 u_int8_t cdb_length;
2853 u_int8_t sense_length;
2854 u_int8_t reserved[2];
2855 u_int8_t cdb[16];
2856 u_int8_t sense[64];
2857 } __packed cdbSense;
2858
2859 struct mrsas_evtarg_ld ld;
2860
2861 struct {
2862 struct mrsas_evtarg_ld ld;
2863 u_int64_t count;
2864 } __packed ld_count;
2865
2866 struct {
2867 u_int64_t lba;
2868 struct mrsas_evtarg_ld ld;
2869 } __packed ld_lba;
2870
2871 struct {
2872 struct mrsas_evtarg_ld ld;
2873 u_int32_t prevOwner;
2874 u_int32_t newOwner;
2875 } __packed ld_owner;
2876
2877 struct {
2878 u_int64_t ld_lba;
2879 u_int64_t pd_lba;
2880 struct mrsas_evtarg_ld ld;
2881 struct mrsas_evtarg_pd pd;
2882 } __packed ld_lba_pd_lba;
2883
2884 struct {
2885 struct mrsas_evtarg_ld ld;
2886 struct mrsas_progress prog;
2887 } __packed ld_prog;
2888
2889 struct {
2890 struct mrsas_evtarg_ld ld;
2891 u_int32_t prev_state;
2892 u_int32_t new_state;
2893 } __packed ld_state;
2894
2895 struct {
2896 u_int64_t strip;
2897 struct mrsas_evtarg_ld ld;
2898 } __packed ld_strip;
2899
2900 struct mrsas_evtarg_pd pd;
2901
2902 struct {
2903 struct mrsas_evtarg_pd pd;
2904 u_int32_t err;
2905 } __packed pd_err;
2906
2907 struct {
2908 u_int64_t lba;
2909 struct mrsas_evtarg_pd pd;
2910 } __packed pd_lba;
2911
2912 struct {
2913 u_int64_t lba;
2914 struct mrsas_evtarg_pd pd;
2915 struct mrsas_evtarg_ld ld;
2916 } __packed pd_lba_ld;
2917
2918 struct {
2919 struct mrsas_evtarg_pd pd;
2920 struct mrsas_progress prog;
2921 } __packed pd_prog;
2922
2923 struct {
2924 struct mrsas_evtarg_pd pd;
2925 u_int32_t prevState;
2926 u_int32_t newState;
2927 } __packed pd_state;
2928
2929 struct {
2930 u_int16_t vendorId;
2931 u_int16_t deviceId;
2932 u_int16_t subVendorId;
2933 u_int16_t subDeviceId;
2934 } __packed pci;
2935
2936 u_int32_t rate;
2937 char str[96];
2938
2939 struct {
2940 u_int32_t rtc;
2941 u_int32_t elapsedSeconds;
2942 } __packed time;
2943
2944 struct {
2945 u_int32_t ecar;
2946 u_int32_t elog;
2947 char str[64];
2948 } __packed ecc;
2949
2950 u_int8_t b[96];
2951 u_int16_t s[48];
2952 u_int32_t w[24];
2953 u_int64_t d[12];
2954 } args;
2955
2956 char description[128];
2957
2958 } __packed;
2959
2960 struct mrsas_irq_context {
2961 struct mrsas_softc *sc;
2962 uint32_t MSIxIndex;
2963 };
2964
2965 enum MEGASAS_OCR_REASON {
2966 FW_FAULT_OCR = 0,
2967 MFI_DCMD_TIMEOUT_OCR = 1,
2968 };
2969
2970 /* Controller management info added to support Linux Emulator */
2971 #define MAX_MGMT_ADAPTERS 1024
2972
2973 struct mrsas_mgmt_info {
2974 u_int16_t count;
2975 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2976 int max_index;
2977 };
2978
2979 #define PCI_TYPE0_ADDRESSES 6
2980 #define PCI_TYPE1_ADDRESSES 2
2981 #define PCI_TYPE2_ADDRESSES 5
2982
2983 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
2984 u_int16_t vendorID;
2985 //(ro)
2986 u_int16_t deviceID;
2987 //(ro)
2988 u_int16_t command;
2989 //Device control
2990 u_int16_t status;
2991 u_int8_t revisionID;
2992 //(ro)
2993 u_int8_t progIf;
2994 //(ro)
2995 u_int8_t subClass;
2996 //(ro)
2997 u_int8_t baseClass;
2998 //(ro)
2999 u_int8_t cacheLineSize;
3000 //(ro +)
3001 u_int8_t latencyTimer;
3002 //(ro +)
3003 u_int8_t headerType;
3004 //(ro)
3005 u_int8_t bist;
3006 //Built in self test
3007
3008 union {
3009 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
3010 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
3011 u_int32_t cis;
3012 u_int16_t subVendorID;
3013 u_int16_t subSystemID;
3014 u_int32_t romBaseAddress;
3015 u_int8_t capabilitiesPtr;
3016 u_int8_t reserved1[3];
3017 u_int32_t reserved2;
3018 u_int8_t interruptLine;
3019 u_int8_t interruptPin;
3020 //(ro)
3021 u_int8_t minimumGrant;
3022 //(ro)
3023 u_int8_t maximumLatency;
3024 //(ro)
3025 } type0;
3026
3027 /*
3028 * PCI to PCI Bridge
3029 */
3030
3031 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
3032 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
3033 u_int8_t primaryBus;
3034 u_int8_t secondaryBus;
3035 u_int8_t subordinateBus;
3036 u_int8_t secondaryLatency;
3037 u_int8_t ioBase;
3038 u_int8_t ioLimit;
3039 u_int16_t secondaryStatus;
3040 u_int16_t memoryBase;
3041 u_int16_t memoryLimit;
3042 u_int16_t prefetchBase;
3043 u_int16_t prefetchLimit;
3044 u_int32_t prefetchBaseUpper32;
3045 u_int32_t prefetchLimitUpper32;
3046 u_int16_t ioBaseUpper16;
3047 u_int16_t ioLimitUpper16;
3048 u_int8_t capabilitiesPtr;
3049 u_int8_t reserved1[3];
3050 u_int32_t romBaseAddress;
3051 u_int8_t interruptLine;
3052 u_int8_t interruptPin;
3053 u_int16_t bridgeControl;
3054 } type1;
3055
3056 /*
3057 * PCI to CARDBUS Bridge
3058 */
3059
3060 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
3061 u_int32_t socketRegistersBaseAddress;
3062 u_int8_t capabilitiesPtr;
3063 u_int8_t reserved;
3064 u_int16_t secondaryStatus;
3065 u_int8_t primaryBus;
3066 u_int8_t secondaryBus;
3067 u_int8_t subordinateBus;
3068 u_int8_t secondaryLatency;
3069 struct {
3070 u_int32_t base;
3071 u_int32_t limit;
3072 } range [PCI_TYPE2_ADDRESSES - 1];
3073 u_int8_t interruptLine;
3074 u_int8_t interruptPin;
3075 u_int16_t bridgeControl;
3076 } type2;
3077 } u;
3078
3079 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
3080
3081 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes
3082
3083 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
3084 union {
3085 struct {
3086 #if _BYTE_ORDER == _LITTLE_ENDIAN
3087 u_int32_t linkSpeed:4;
3088 u_int32_t linkWidth:6;
3089 u_int32_t aspmSupport:2;
3090 u_int32_t losExitLatency:3;
3091 u_int32_t l1ExitLatency:3;
3092 u_int32_t rsvdp:6;
3093 u_int32_t portNumber:8;
3094 #else
3095 u_int32_t portNumber:8;
3096 u_int32_t rsvdp:6;
3097 u_int32_t l1ExitLatency:3;
3098 u_int32_t losExitLatency:3;
3099 u_int32_t aspmSupport:2;
3100 u_int32_t linkWidth:6;
3101 u_int32_t linkSpeed:4;
3102 #endif
3103 } bits;
3104
3105 u_int32_t asUlong;
3106 } u;
3107 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
3108
3109 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
3110
3111 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
3112 union {
3113 struct {
3114 #if _BYTE_ORDER == _LITTLE_ENDIAN
3115 u_int16_t linkSpeed:4;
3116 u_int16_t negotiatedLinkWidth:6;
3117 u_int16_t linkTrainingError:1;
3118 u_int16_t linkTraning:1;
3119 u_int16_t slotClockConfig:1;
3120 u_int16_t rsvdZ:3;
3121 #else
3122 u_int16_t rsvdZ:3;
3123 u_int16_t slotClockConfig:1;
3124 u_int16_t linkTraning:1;
3125 u_int16_t linkTrainingError:1;
3126 u_int16_t negotiatedLinkWidth:6;
3127 u_int16_t linkSpeed:4;
3128 #endif
3129 } bits;
3130
3131 u_int16_t asUshort;
3132 } u;
3133 u_int16_t reserved;
3134 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
3135
3136 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
3137
3138 typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
3139 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
3140 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
3141 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
3142
3143 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
3144
3145 /* PCI information */
3146 typedef struct _MRSAS_DRV_PCI_INFORMATION {
3147 u_int32_t busNumber;
3148 u_int8_t deviceNumber;
3149 u_int8_t functionNumber;
3150 u_int8_t interruptVector;
3151 u_int8_t reserved1;
3152 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
3153 MRSAS_DRV_PCI_CAPABILITIES capability;
3154 u_int32_t domainID;
3155 u_int8_t reserved2[28];
3156 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
3157
3158 typedef enum _MR_PD_TYPE {
3159 UNKNOWN_DRIVE = 0,
3160 PARALLEL_SCSI = 1,
3161 SAS_PD = 2,
3162 SATA_PD = 3,
3163 FC_PD = 4,
3164 NVME_PD = 5,
3165 } MR_PD_TYPE;
3166
3167 typedef union _MR_PD_REF {
3168 struct {
3169 u_int16_t deviceId;
3170 u_int16_t seqNum;
3171 } mrPdRef;
3172 u_int32_t ref;
3173 } MR_PD_REF;
3174
3175 /*
3176 * define the DDF Type bit structure
3177 */
3178 union MR_PD_DDF_TYPE {
3179 struct {
3180 union {
3181 struct {
3182 #if _BYTE_ORDER == _LITTLE_ENDIAN
3183 u_int16_t forcedPDGUID:1;
3184 u_int16_t inVD:1;
3185 u_int16_t isGlobalSpare:1;
3186 u_int16_t isSpare:1;
3187 u_int16_t isForeign:1;
3188 u_int16_t reserved:7;
3189 u_int16_t intf:4;
3190 #else
3191 u_int16_t intf:4;
3192 u_int16_t reserved:7;
3193 u_int16_t isForeign:1;
3194 u_int16_t isSpare:1;
3195 u_int16_t isGlobalSpare:1;
3196 u_int16_t inVD:1;
3197 u_int16_t forcedPDGUID:1;
3198 #endif
3199 } pdType;
3200 u_int16_t type;
3201 };
3202 u_int16_t reserved;
3203 } ddf;
3204 struct {
3205 u_int32_t reserved;
3206 } nonDisk;
3207 u_int32_t type;
3208 } __packed;
3209
3210 /*
3211 * defines the progress structure
3212 */
3213 union MR_PROGRESS {
3214 struct {
3215 u_int16_t progress;
3216 union {
3217 u_int16_t elapsedSecs;
3218 u_int16_t elapsedSecsForLastPercent;
3219 };
3220 } mrProgress;
3221 u_int32_t w;
3222 } __packed;
3223
3224 /*
3225 * defines the physical drive progress structure
3226 */
3227 struct MR_PD_PROGRESS {
3228 struct {
3229 #if _BYTE_ORDER == _LITTLE_ENDIAN
3230 u_int32_t rbld:1;
3231 u_int32_t patrol:1;
3232 u_int32_t clear:1;
3233 u_int32_t copyBack:1;
3234 u_int32_t erase:1;
3235 u_int32_t locate:1;
3236 u_int32_t reserved:26;
3237 #else
3238 u_int32_t reserved:26;
3239 u_int32_t locate:1;
3240 u_int32_t erase:1;
3241 u_int32_t copyBack:1;
3242 u_int32_t clear:1;
3243 u_int32_t patrol:1;
3244 u_int32_t rbld:1;
3245 #endif
3246 } active;
3247 union MR_PROGRESS rbld;
3248 union MR_PROGRESS patrol;
3249 union {
3250 union MR_PROGRESS clear;
3251 union MR_PROGRESS erase;
3252 };
3253
3254 struct {
3255 #if _BYTE_ORDER == _LITTLE_ENDIAN
3256 u_int32_t rbld:1;
3257 u_int32_t patrol:1;
3258 u_int32_t clear:1;
3259 u_int32_t copyBack:1;
3260 u_int32_t erase:1;
3261 u_int32_t reserved:27;
3262 #else
3263 u_int32_t reserved:27;
3264 u_int32_t erase:1;
3265 u_int32_t copyBack:1;
3266 u_int32_t clear:1;
3267 u_int32_t patrol:1;
3268 u_int32_t rbld:1;
3269 #endif
3270 } pause;
3271
3272 union MR_PROGRESS reserved[3];
3273 } __packed;
3274
3275 struct mrsas_pd_info {
3276 MR_PD_REF ref;
3277 u_int8_t inquiryData[96];
3278 u_int8_t vpdPage83[64];
3279
3280 u_int8_t notSupported;
3281 u_int8_t scsiDevType;
3282
3283 union {
3284 u_int8_t connectedPortBitmap;
3285 u_int8_t connectedPortNumbers;
3286 };
3287
3288 u_int8_t deviceSpeed;
3289 u_int32_t mediaErrCount;
3290 u_int32_t otherErrCount;
3291 u_int32_t predFailCount;
3292 u_int32_t lastPredFailEventSeqNum;
3293
3294 u_int16_t fwState;
3295 u_int8_t disabledForRemoval;
3296 u_int8_t linkSpeed;
3297 union MR_PD_DDF_TYPE state;
3298
3299 struct {
3300 u_int8_t count;
3301 #if _BYTE_ORDER == _LITTLE_ENDIAN
3302 u_int8_t isPathBroken:4;
3303 u_int8_t reserved3:3;
3304 u_int8_t widePortCapable:1;
3305 #else
3306 u_int8_t widePortCapable:1;
3307 u_int8_t reserved3:3;
3308 u_int8_t isPathBroken:4;
3309 #endif
3310 u_int8_t connectorIndex[2];
3311 u_int8_t reserved[4];
3312 u_int64_t sasAddr[2];
3313 u_int8_t reserved2[16];
3314 } pathInfo;
3315
3316 u_int64_t rawSize;
3317 u_int64_t nonCoercedSize;
3318 u_int64_t coercedSize;
3319 u_int16_t enclDeviceId;
3320 u_int8_t enclIndex;
3321
3322 union {
3323 u_int8_t slotNumber;
3324 u_int8_t enclConnectorIndex;
3325 };
3326
3327 struct MR_PD_PROGRESS progInfo;
3328 u_int8_t badBlockTableFull;
3329 u_int8_t unusableInCurrentConfig;
3330 u_int8_t vpdPage83Ext[64];
3331 u_int8_t powerState;
3332 u_int8_t enclPosition;
3333 u_int32_t allowedOps;
3334 u_int16_t copyBackPartnerId;
3335 u_int16_t enclPartnerDeviceId;
3336 struct {
3337 #if _BYTE_ORDER == _LITTLE_ENDIAN
3338 u_int16_t fdeCapable:1;
3339 u_int16_t fdeEnabled:1;
3340 u_int16_t secured:1;
3341 u_int16_t locked:1;
3342 u_int16_t foreign:1;
3343 u_int16_t needsEKM:1;
3344 u_int16_t reserved:10;
3345 #else
3346 u_int16_t reserved:10;
3347 u_int16_t needsEKM:1;
3348 u_int16_t foreign:1;
3349 u_int16_t locked:1;
3350 u_int16_t secured:1;
3351 u_int16_t fdeEnabled:1;
3352 u_int16_t fdeCapable:1;
3353 #endif
3354 } security;
3355 u_int8_t mediaType;
3356 u_int8_t notCertified;
3357 u_int8_t bridgeVendor[8];
3358 u_int8_t bridgeProductIdentification[16];
3359 u_int8_t bridgeProductRevisionLevel[4];
3360 u_int8_t satBridgeExists;
3361
3362 u_int8_t interfaceType;
3363 u_int8_t temperature;
3364 u_int8_t emulatedBlockSize;
3365 u_int16_t userDataBlockSize;
3366 u_int16_t reserved2;
3367
3368 struct {
3369 #if _BYTE_ORDER == _LITTLE_ENDIAN
3370 u_int32_t piType:3;
3371 u_int32_t piFormatted:1;
3372 u_int32_t piEligible:1;
3373 u_int32_t NCQ:1;
3374 u_int32_t WCE:1;
3375 u_int32_t commissionedSpare:1;
3376 u_int32_t emergencySpare:1;
3377 u_int32_t ineligibleForSSCD:1;
3378 u_int32_t ineligibleForLd:1;
3379 u_int32_t useSSEraseType:1;
3380 u_int32_t wceUnchanged:1;
3381 u_int32_t supportScsiUnmap:1;
3382 u_int32_t reserved:18;
3383 #else
3384 u_int32_t reserved:18;
3385 u_int32_t supportScsiUnmap:1;
3386 u_int32_t wceUnchanged:1;
3387 u_int32_t useSSEraseType:1;
3388 u_int32_t ineligibleForLd:1;
3389 u_int32_t ineligibleForSSCD:1;
3390 u_int32_t emergencySpare:1;
3391 u_int32_t commissionedSpare:1;
3392 u_int32_t WCE:1;
3393 u_int32_t NCQ:1;
3394 u_int32_t piEligible:1;
3395 u_int32_t piFormatted:1;
3396 u_int32_t piType:3;
3397 #endif
3398 } properties;
3399
3400 u_int64_t shieldDiagCompletionTime;
3401 u_int8_t shieldCounter;
3402
3403 u_int8_t linkSpeedOther;
3404 u_int8_t reserved4[2];
3405
3406 struct {
3407 #if _BYTE_ORDER == _LITTLE_ENDIAN
3408 u_int32_t bbmErrCountSupported:1;
3409 u_int32_t bbmErrCount:31;
3410 #else
3411 u_int32_t bbmErrCount:31;
3412 u_int32_t bbmErrCountSupported:1;
3413 #endif
3414 } bbmErr;
3415
3416 u_int8_t reserved1[512-428];
3417 } __packed;
3418
3419 struct mrsas_target {
3420 u_int16_t target_id;
3421 u_int32_t queue_depth;
3422 u_int8_t interface_type;
3423 u_int32_t max_io_size_kb;
3424 } __packed;
3425
3426 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
3427 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
3428 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
3429
3430 /*******************************************************************
3431 * per-instance data
3432 ********************************************************************/
3433 struct mrsas_softc {
3434 device_t mrsas_dev;
3435 struct cdev *mrsas_cdev;
3436 struct intr_config_hook mrsas_ich;
3437 struct cdev *mrsas_linux_emulator_cdev;
3438 uint16_t device_id;
3439 struct resource *reg_res;
3440 int reg_res_id;
3441 bus_space_tag_t bus_tag;
3442 bus_space_handle_t bus_handle;
3443 bus_dma_tag_t mrsas_parent_tag;
3444 bus_dma_tag_t verbuf_tag;
3445 bus_dmamap_t verbuf_dmamap;
3446 void *verbuf_mem;
3447 bus_addr_t verbuf_phys_addr;
3448 bus_dma_tag_t sense_tag;
3449 bus_dmamap_t sense_dmamap;
3450 void *sense_mem;
3451 bus_addr_t sense_phys_addr;
3452 bus_dma_tag_t io_request_tag;
3453 bus_dmamap_t io_request_dmamap;
3454 void *io_request_mem;
3455 bus_addr_t io_request_phys_addr;
3456 bus_dma_tag_t chain_frame_tag;
3457 bus_dmamap_t chain_frame_dmamap;
3458 void *chain_frame_mem;
3459 bus_addr_t chain_frame_phys_addr;
3460 bus_dma_tag_t reply_desc_tag;
3461 bus_dmamap_t reply_desc_dmamap;
3462 void *reply_desc_mem;
3463 bus_addr_t reply_desc_phys_addr;
3464 bus_dma_tag_t ioc_init_tag;
3465 bus_dmamap_t ioc_init_dmamap;
3466 void *ioc_init_mem;
3467 bus_addr_t ioc_init_phys_mem;
3468 bus_dma_tag_t data_tag;
3469 struct cam_sim *sim_0;
3470 struct cam_sim *sim_1;
3471 struct cam_path *path_0;
3472 struct cam_path *path_1;
3473 struct mtx sim_lock;
3474 struct mtx pci_lock;
3475 struct mtx io_lock;
3476 struct mtx ioctl_lock;
3477 struct mtx mpt_cmd_pool_lock;
3478 struct mtx mfi_cmd_pool_lock;
3479 struct mtx raidmap_lock;
3480 struct mtx aen_lock;
3481 struct mtx stream_lock;
3482 struct selinfo mrsas_select;
3483 uint32_t mrsas_aen_triggered;
3484 uint32_t mrsas_poll_waiting;
3485
3486 struct sema ioctl_count_sema;
3487 uint32_t max_fw_cmds;
3488 uint16_t max_scsi_cmds;
3489 uint32_t max_num_sge;
3490 struct resource *mrsas_irq[MAX_MSIX_COUNT];
3491 void *intr_handle[MAX_MSIX_COUNT];
3492 int irq_id[MAX_MSIX_COUNT];
3493 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT];
3494 int msix_vectors;
3495 int msix_enable;
3496 uint32_t msix_reg_offset[16];
3497 uint8_t mask_interrupts;
3498 uint16_t max_chain_frame_sz;
3499 struct mrsas_mpt_cmd **mpt_cmd_list;
3500 struct mrsas_mfi_cmd **mfi_cmd_list;
3501 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
3502 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
3503 bus_addr_t req_frames_desc_phys;
3504 u_int8_t *req_frames_desc;
3505 u_int8_t *req_desc;
3506 bus_addr_t io_request_frames_phys;
3507 u_int8_t *io_request_frames;
3508 bus_addr_t reply_frames_desc_phys;
3509 u_int16_t last_reply_idx[MAX_MSIX_COUNT];
3510 u_int32_t reply_q_depth;
3511 u_int32_t request_alloc_sz;
3512 u_int32_t reply_alloc_sz;
3513 u_int32_t io_frames_alloc_sz;
3514 u_int32_t chain_frames_alloc_sz;
3515 u_int16_t max_sge_in_main_msg;
3516 u_int16_t max_sge_in_chain;
3517 u_int8_t chain_offset_io_request;
3518 u_int8_t chain_offset_mfi_pthru;
3519 u_int32_t map_sz;
3520 u_int64_t map_id;
3521 u_int64_t pd_seq_map_id;
3522 struct mrsas_mfi_cmd *map_update_cmd;
3523 struct mrsas_mfi_cmd *jbod_seq_cmd;
3524 struct mrsas_mfi_cmd *aen_cmd;
3525 u_int8_t fast_path_io;
3526 void *chan;
3527 void *ocr_chan;
3528 u_int8_t adprecovery;
3529 u_int8_t remove_in_progress;
3530 u_int8_t ocr_thread_active;
3531 u_int8_t do_timedout_reset;
3532 u_int32_t reset_in_progress;
3533 u_int32_t reset_count;
3534 u_int32_t block_sync_cache;
3535 u_int32_t drv_stream_detection;
3536 u_int8_t fw_sync_cache_support;
3537 mrsas_atomic_t target_reset_outstanding;
3538 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS)
3539 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS];
3540
3541 bus_dma_tag_t jbodmap_tag[2];
3542 bus_dmamap_t jbodmap_dmamap[2];
3543 void *jbodmap_mem[2];
3544 bus_addr_t jbodmap_phys_addr[2];
3545
3546 bus_dma_tag_t raidmap_tag[2];
3547 bus_dmamap_t raidmap_dmamap[2];
3548 void *raidmap_mem[2];
3549 bus_addr_t raidmap_phys_addr[2];
3550 bus_dma_tag_t mficmd_frame_tag;
3551 bus_dma_tag_t mficmd_sense_tag;
3552 bus_addr_t evt_detail_phys_addr;
3553 bus_dma_tag_t evt_detail_tag;
3554 bus_dmamap_t evt_detail_dmamap;
3555 struct mrsas_evt_detail *evt_detail_mem;
3556 bus_addr_t pd_info_phys_addr;
3557 bus_dma_tag_t pd_info_tag;
3558 bus_dmamap_t pd_info_dmamap;
3559 struct mrsas_pd_info *pd_info_mem;
3560 struct mrsas_ctrl_info *ctrl_info;
3561 bus_dma_tag_t ctlr_info_tag;
3562 bus_dmamap_t ctlr_info_dmamap;
3563 void *ctlr_info_mem;
3564 bus_addr_t ctlr_info_phys_addr;
3565 u_int32_t max_sectors_per_req;
3566 u_int32_t disableOnlineCtrlReset;
3567 mrsas_atomic_t fw_outstanding;
3568 mrsas_atomic_t prp_count;
3569 mrsas_atomic_t sge_holes;
3570
3571 u_int32_t mrsas_debug;
3572 u_int32_t mrsas_io_timeout;
3573 u_int32_t mrsas_fw_fault_check_delay;
3574 u_int32_t io_cmds_highwater;
3575 u_int8_t UnevenSpanSupport;
3576 struct sysctl_ctx_list sysctl_ctx;
3577 struct sysctl_oid *sysctl_tree;
3578 struct proc *ocr_thread;
3579 u_int32_t last_seq_num;
3580 bus_dma_tag_t el_info_tag;
3581 bus_dmamap_t el_info_dmamap;
3582 void *el_info_mem;
3583 bus_addr_t el_info_phys_addr;
3584 struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
3585 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
3586 struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS];
3587 u_int8_t ld_ids[MRSAS_MAX_LD_IDS];
3588 struct taskqueue *ev_tq;
3589 struct task ev_task;
3590 u_int32_t CurLdCount;
3591 u_int64_t reset_flags;
3592 int lb_pending_cmds;
3593 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
3594 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
3595
3596 u_int8_t mrsas_gen3_ctrl;
3597 u_int8_t secure_jbod_support;
3598 u_int8_t use_seqnum_jbod_fp;
3599 /* FW suport for more than 256 PD/JBOD */
3600 u_int32_t support_morethan256jbod;
3601 u_int8_t max256vdSupport;
3602 u_int16_t fw_supported_vd_count;
3603 u_int16_t fw_supported_pd_count;
3604
3605 u_int16_t drv_supported_vd_count;
3606 u_int16_t drv_supported_pd_count;
3607
3608 u_int32_t max_map_sz;
3609 u_int32_t current_map_sz;
3610 u_int32_t old_map_sz;
3611 u_int32_t new_map_sz;
3612 u_int32_t drv_map_sz;
3613
3614 u_int32_t nvme_page_size;
3615 boolean_t is_ventura;
3616 boolean_t is_aero;
3617 boolean_t msix_combined;
3618 boolean_t atomic_desc_support;
3619 u_int16_t maxRaidMapSize;
3620
3621 /* Non dma-able memory. Driver local copy. */
3622 MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
3623 PTR_LD_STREAM_DETECT *streamDetectByLD;
3624 };
3625
3626 /* Compatibility shims for different OS versions */
3627 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
3628 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
3629 #define mrsas_kproc_exit(arg) kproc_exit(arg)
3630
3631 static __inline void
mrsas_clear_bit(int b,volatile void * p)3632 mrsas_clear_bit(int b, volatile void *p)
3633 {
3634 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
3635 }
3636
3637 static __inline void
mrsas_set_bit(int b,volatile void * p)3638 mrsas_set_bit(int b, volatile void *p)
3639 {
3640 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
3641 }
3642
3643 static __inline int
mrsas_test_bit(int b,volatile void * p)3644 mrsas_test_bit(int b, volatile void *p)
3645 {
3646 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
3647 }
3648
3649 #include "mrsas_ioctl.h"
3650 extern int mrsas_user_command(struct mrsas_softc *, struct mfi_ioc_passthru *);
3651
3652 #endif /* MRSAS_H */
3653