1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation and/or other 15 * materials provided with the distribution. 16 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 * 32 * The views and conclusions contained in the software and documentation are 33 * those of the authors and should not be interpreted as representing 34 * official policies,either expressed or implied, of the FreeBSD Project. 35 * 36 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 37 * 38 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 39 * 40 */ 41 42 #ifndef MPI30_CNFG_H 43 #define MPI30_CNFG_H 1 44 45 /***************************************************************************** 46 * Configuration Page Types * 47 ****************************************************************************/ 48 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 49 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 50 #define MPI3_CONFIG_PAGETYPE_IOC (0x02) 51 #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) 52 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 53 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 54 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 55 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 56 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 57 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 58 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 59 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 60 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 61 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 62 63 /***************************************************************************** 64 * Configuration Page Attributes * 65 ****************************************************************************/ 66 #define MPI3_CONFIG_PAGEATTR_MASK (0xF0) 67 #define MPI3_CONFIG_PAGEATTR_SHIFT (4) 68 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 69 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 70 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 71 72 /***************************************************************************** 73 * Configuration Page Actions * 74 ****************************************************************************/ 75 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 76 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 77 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 78 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 79 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 80 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 81 82 /***************************************************************************** 83 * Configuration Page Addressing * 84 ****************************************************************************/ 85 86 /**** Device PageAddress Format ****/ 87 #define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000) 88 #define MPI3_DEVICE_PGAD_FORM_SHIFT (28) 89 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 90 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 91 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 92 #define MPI3_DEVICE_PGAD_HANDLE_SHIFT (0) 93 94 /**** SAS Expander PageAddress Format ****/ 95 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 96 #define MPI3_SAS_EXPAND_PGAD_FORM_SHIFT (28) 97 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 98 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 99 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 100 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 101 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 102 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 103 #define MPI3_SAS_EXPAND_PGAD_HANDLE_SHIFT (0) 104 105 /**** SAS Phy PageAddress Format ****/ 106 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 107 #define MPI3_SAS_PHY_PGAD_FORM_SHIFT (28) 108 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 109 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 110 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 111 112 /**** SAS Port PageAddress Format ****/ 113 #define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000) 114 #define MPI3_SASPORT_PGAD_FORM_SHIFT (28) 115 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 116 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 117 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF) 118 #define MPI3_SASPORT_PGAD_PORT_NUMBER_SHIFT (0) 119 120 /**** Enclosure PageAddress Format ****/ 121 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000) 122 #define MPI3_ENCLOS_PGAD_FORM_SHIFT (28) 123 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 124 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 125 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 126 #define MPI3_ENCLOS_PGAD_HANDLE_SHIFT (0) 127 128 /**** PCIe Switch PageAddress Format ****/ 129 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 130 #define MPI3_PCIE_SWITCH_PGAD_FORM_SHIFT (28) 131 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 132 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 133 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 134 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 135 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 136 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 137 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_SHIFT (0) 138 139 /**** PCIe Link PageAddress Format ****/ 140 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 141 #define MPI3_PCIE_LINK_PGAD_FORM_SHIFT (28) 142 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 143 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 144 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF) 145 #define MPI3_PCIE_LINK_PGAD_LINKNUM_SHIFT (0) 146 147 /**** Security PageAddress Format ****/ 148 #define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000) 149 #define MPI3_SECURITY_PGAD_FORM_SHIFT (28) 150 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 151 #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) 152 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00) 153 #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) 154 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF) 155 #define MPI3_SECURITY_PGAD_SLOT_SHIFT (0) 156 157 /**** Instance PageAddress Format ****/ 158 #define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000FFFF) 159 #define MPI3_INSTANCE_PGAD_INSTANCE_SHIFT (0) 160 161 162 /***************************************************************************** 163 * Configuration Request Message * 164 ****************************************************************************/ 165 typedef struct _MPI3_CONFIG_REQUEST 166 { 167 U16 HostTag; /* 0x00 */ 168 U8 IOCUseOnly02; /* 0x02 */ 169 U8 Function; /* 0x03 */ 170 U16 IOCUseOnly04; /* 0x04 */ 171 U8 IOCUseOnly06; /* 0x06 */ 172 U8 MsgFlags; /* 0x07 */ 173 U16 ChangeCount; /* 0x08 */ 174 U8 ProxyIOCNumber; /* 0x0A */ 175 U8 Reserved0B; /* 0x0B */ 176 U8 PageVersion; /* 0x0C */ 177 U8 PageNumber; /* 0x0D */ 178 U8 PageType; /* 0x0E */ 179 U8 Action; /* 0x0F */ 180 U32 PageAddress; /* 0x10 */ 181 U16 PageLength; /* 0x14 */ 182 U16 Reserved16; /* 0x16 */ 183 U32 Reserved18[2]; /* 0x18 */ 184 MPI3_SGE_UNION SGL; /* 0x20 */ 185 } MPI3_CONFIG_REQUEST, MPI3_POINTER PTR_MPI3_CONFIG_REQUEST, 186 Mpi3ConfigRequest_t, MPI3_POINTER pMpi3ConfigRequest_t; 187 188 /***************************************************************************** 189 * Configuration Pages * 190 ****************************************************************************/ 191 192 /***************************************************************************** 193 * Configuration Page Header * 194 ****************************************************************************/ 195 typedef struct _MPI3_CONFIG_PAGE_HEADER 196 { 197 U8 PageVersion; /* 0x00 */ 198 U8 Reserved01; /* 0x01 */ 199 U8 PageNumber; /* 0x02 */ 200 U8 PageAttribute; /* 0x03 */ 201 U16 PageLength; /* 0x04 */ 202 U8 PageType; /* 0x06 */ 203 U8 Reserved07; /* 0x07 */ 204 } MPI3_CONFIG_PAGE_HEADER, MPI3_POINTER PTR_MPI3_CONFIG_PAGE_HEADER, 205 Mpi3ConfigPageHeader_t, MPI3_POINTER pMpi3ConfigPageHeader_t; 206 207 /***************************************************************************** 208 * Common definitions used by Configuration Pages * 209 ****************************************************************************/ 210 211 /**** Defines for NegotiatedLinkRates ****/ 212 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xF0) 213 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 214 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0F) 215 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) 216 /*** Below defines are used in both the PhysicalLinkRate and ***/ 217 /*** LogicalLinkRate fields above. ***/ 218 /*** (by applying the proper _SHIFT value) ***/ 219 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 220 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 221 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 222 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 223 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 224 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 225 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 226 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 227 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 228 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0A) 229 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0B) 230 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0C) 231 232 /**** Defines for the AttachedPhyInfo field ****/ 233 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 234 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 235 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 236 237 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000F) 238 #define MPI3_SAS_APHYINFO_REASON_SHIFT (0) 239 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 240 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 241 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 242 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 243 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 244 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 245 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 246 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 247 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 248 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 249 250 /**** Defines for the PhyInfo field ****/ 251 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xC0000000) 252 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 253 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 254 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 255 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 256 257 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 258 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SHIFT (27) 259 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 260 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 261 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 262 263 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) 264 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) 265 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) 266 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) 267 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) 268 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) 269 270 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 271 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) 272 #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 273 274 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000F0000) 275 #define MPI3_SAS_PHYINFO_REASON_SHIFT (16) 276 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 277 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 278 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 279 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 280 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 281 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 282 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 283 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 284 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 285 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 286 287 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 288 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 289 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 290 291 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000F00) 292 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 293 294 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000F0) 295 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SHIFT (4) 296 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 297 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 298 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 299 300 /**** Defines for the ProgrammedLinkRate field ****/ 301 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xF0) 302 #define MPI3_SAS_PRATE_MAX_RATE_SHIFT (4) 303 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 304 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 305 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 306 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xA0) 307 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xB0) 308 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xC0) 309 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0F) 310 #define MPI3_SAS_PRATE_MIN_RATE_SHIFT (0) 311 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 312 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 313 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 314 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0A) 315 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0B) 316 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0C) 317 318 /**** Defines for the HwLinkRate field ****/ 319 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xF0) 320 #define MPI3_SAS_HWRATE_MAX_RATE_SHIFT (4) 321 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 322 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 323 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 324 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 325 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 326 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0F) 327 #define MPI3_SAS_HWRATE_MIN_RATE_SHIFT (0) 328 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 329 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 330 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 331 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 332 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 333 334 /**** Defines for the Slot field ****/ 335 #define MPI3_SLOT_INVALID (0xFFFF) 336 337 /**** Defines for the SlotIndex field ****/ 338 #define MPI3_SLOT_INDEX_INVALID (0xFFFF) 339 340 /**** Defines for the LinkChangeCount fields ****/ 341 #define MPI3_LINK_CHANGE_COUNT_INVALID (0xFFFF) 342 343 /**** Defines for the RateChangeCount fields ****/ 344 #define MPI3_RATE_CHANGE_COUNT_INVALID (0xFFFF) 345 346 /**** Defines for the Temp Sensor Location field ****/ 347 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) 348 #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) 349 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) 350 #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) 351 352 /***************************************************************************** 353 * Manufacturing Configuration Pages * 354 ****************************************************************************/ 355 356 #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) 357 358 /* MPI v3.0 SAS Products */ 359 #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00A5) 360 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00B3) 361 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00B4) 362 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_NS (0x00B5) 363 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_NS (0x00B6) 364 #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00B8) 365 #define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00F0) 366 #define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00F1) 367 #define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00F2) 368 369 /***************************************************************************** 370 * Manufacturing Page 0 * 371 ****************************************************************************/ 372 typedef struct _MPI3_MAN_PAGE0 373 { 374 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 375 U8 ChipRevision[8]; /* 0x08 */ 376 U8 ChipName[32]; /* 0x10 */ 377 U8 BoardName[32]; /* 0x30 */ 378 U8 BoardAssembly[32]; /* 0x50 */ 379 U8 BoardTracerNumber[32]; /* 0x70 */ 380 U32 BoardPower; /* 0x90 */ 381 U32 Reserved94; /* 0x94 */ 382 U32 Reserved98; /* 0x98 */ 383 U8 OEM; /* 0x9C */ 384 U8 ProfileIdentifier; /* 0x9D */ 385 U16 Flags; /* 0x9E */ 386 U8 BoardMfgDay; /* 0xA0 */ 387 U8 BoardMfgMonth; /* 0xA1 */ 388 U16 BoardMfgYear; /* 0xA2 */ 389 U8 BoardReworkDay; /* 0xA4 */ 390 U8 BoardReworkMonth; /* 0xA5 */ 391 U16 BoardReworkYear; /* 0xA6 */ 392 U8 BoardRevision[8]; /* 0xA8 */ 393 U8 EPackFRU[16]; /* 0xB0 */ 394 U8 ProductName[256]; /* 0xC0 */ 395 } MPI3_MAN_PAGE0, MPI3_POINTER PTR_MPI3_MAN_PAGE0, 396 Mpi3ManPage0_t, MPI3_POINTER pMpi3ManPage0_t; 397 398 /**** Defines for the PageVersion field ****/ 399 #define MPI3_MAN0_PAGEVERSION (0x00) 400 401 /**** Defines for the Flags field ****/ 402 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) 403 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) 404 405 /***************************************************************************** 406 * Manufacturing Page 1 * 407 ****************************************************************************/ 408 409 #define MPI3_MAN1_VPD_SIZE (512) 410 411 typedef struct _MPI3_MAN_PAGE1 412 { 413 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 414 U32 Reserved08[2]; /* 0x08 */ 415 U8 VPD[MPI3_MAN1_VPD_SIZE]; /* 0x10 */ 416 } MPI3_MAN_PAGE1, MPI3_POINTER PTR_MPI3_MAN_PAGE1, 417 Mpi3ManPage1_t, MPI3_POINTER pMpi3ManPage1_t; 418 419 /**** Defines for the PageVersion field ****/ 420 #define MPI3_MAN1_PAGEVERSION (0x00) 421 422 423 /***************************************************************************** 424 * Manufacturing Page 2 * 425 ****************************************************************************/ 426 427 typedef struct _MPI3_MAN_PAGE2 428 { 429 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 430 U8 Flags; /* 0x08 */ 431 U8 Reserved09[3]; /* 0x09 */ 432 U32 Reserved0C[3]; /* 0x0C */ 433 U8 OEMBoardTracerNumber[32]; /* 0x18 */ 434 } MPI3_MAN_PAGE2, MPI3_POINTER PTR_MPI3_MAN_PAGE2, 435 Mpi3ManPage2_t, MPI3_POINTER pMpi3ManPage2_t; 436 437 /**** Defines for the PageVersion field ****/ 438 #define MPI3_MAN2_PAGEVERSION (0x00) 439 440 /**** Defines for the Flags field ****/ 441 #define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) 442 443 /***************************************************************************** 444 * Manufacturing Page 5 * 445 ****************************************************************************/ 446 typedef struct _MPI3_MAN5_PHY_ENTRY 447 { 448 U64 IOC_WWID; /* 0x00 */ 449 U64 DeviceName; /* 0x08 */ 450 U64 SATA_WWID; /* 0x10 */ 451 } MPI3_MAN5_PHY_ENTRY, MPI3_POINTER PTR_MPI3_MAN5_PHY_ENTRY, 452 Mpi3Man5PhyEntry_t, MPI3_POINTER pMpi3Man5PhyEntry_t; 453 454 #ifndef MPI3_MAN5_PHY_MAX 455 #define MPI3_MAN5_PHY_MAX (1) 456 #endif /* MPI3_MAN5_PHY_MAX */ 457 458 typedef struct _MPI3_MAN_PAGE5 459 { 460 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 461 U8 NumPhys; /* 0x08 */ 462 U8 Reserved09[3]; /* 0x09 */ 463 U32 Reserved0C; /* 0x0C */ 464 MPI3_MAN5_PHY_ENTRY Phy[MPI3_MAN5_PHY_MAX]; /* 0x10 */ 465 } MPI3_MAN_PAGE5, MPI3_POINTER PTR_MPI3_MAN_PAGE5, 466 Mpi3ManPage5_t, MPI3_POINTER pMpi3ManPage5_t; 467 468 /**** Defines for the PageVersion field ****/ 469 #define MPI3_MAN5_PAGEVERSION (0x00) 470 471 /***************************************************************************** 472 * Manufacturing Page 6 * 473 ****************************************************************************/ 474 typedef struct _MPI3_MAN6_GPIO_ENTRY 475 { 476 U8 FunctionCode; /* 0x00 */ 477 U8 FunctionFlags; /* 0x01 */ 478 U16 Flags; /* 0x02 */ 479 U8 Param1; /* 0x04 */ 480 U8 Param2; /* 0x05 */ 481 U16 Reserved06; /* 0x06 */ 482 U32 Param3; /* 0x08 */ 483 } MPI3_MAN6_GPIO_ENTRY, MPI3_POINTER PTR_MPI3_MAN6_GPIO_ENTRY, 484 Mpi3Man6GpioEntry_t, MPI3_POINTER pMpi3Man6GpioEntry_t; 485 486 /**** Defines for the FunctionCode field ****/ 487 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 488 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 489 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 490 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 491 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 492 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 493 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 494 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 495 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 496 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0A) 497 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0B) 498 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0C) 499 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0D) 500 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0E) 501 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0F) 502 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 503 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 504 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 505 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) 506 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) 507 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) 508 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) 509 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) 510 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) 511 #define MPI3_MAN6_GPIO_FUNCTION_MGMT_CONTROLLER_RESET (0x19) 512 513 /**** Defines for FunctionFlags when FunctionCode is ISTWI_RESET ****/ 514 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) 515 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_SHIFT (0) 516 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) 517 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) 518 519 /**** Defines for Param1 (Flags) when FunctionCode is EXT_INTERRUPT ****/ 520 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xF0) 521 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_SHIFT (4) 522 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 523 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 524 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 525 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02) 526 527 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 528 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_SHIFT (0) 529 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 530 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 531 532 /**** Defines for Param1 (LEVEL) when FunctionCode is OVER_TEMPERATURE ****/ 533 #define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00) 534 #define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01) 535 #define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02) 536 537 /**** Defines for Param1 (PHY STATE) when FunctionCode is PORT_STATUS_GREEN ****/ 538 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 539 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 540 541 /**** Defines for Param1 (INTERFACE_SIGNAL) when FunctionCode is CABLE_MANAGEMENT ****/ 542 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 543 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 544 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 545 546 /**** Defines for Param1 (LICENSE_TYPE) when FunctionCode is LICENSE ****/ 547 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 548 549 550 /**** Defines for the Flags field ****/ 551 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 552 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SHIFT (8) 553 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 554 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 555 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00C0) 556 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_SHIFT (6) 557 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 558 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 559 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 560 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00C0) 561 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 562 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 563 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 564 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 565 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 566 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_SHIFT (0) 567 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 568 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 569 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 570 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 571 572 #ifndef MPI3_MAN6_GPIO_MAX 573 #define MPI3_MAN6_GPIO_MAX (1) 574 #endif /* MPI3_MAN6_GPIO_MAX */ 575 576 typedef struct _MPI3_MAN_PAGE6 577 { 578 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 579 U16 Flags; /* 0x08 */ 580 U16 Reserved0A; /* 0x0A */ 581 U8 NumGPIO; /* 0x0C */ 582 U8 Reserved0D[3]; /* 0x0D */ 583 MPI3_MAN6_GPIO_ENTRY GPIO[MPI3_MAN6_GPIO_MAX]; /* 0x10 */ 584 } MPI3_MAN_PAGE6, MPI3_POINTER PTR_MPI3_MAN_PAGE6, 585 Mpi3ManPage6_t, MPI3_POINTER pMpi3ManPage6_t; 586 587 /**** Defines for the PageVersion field ****/ 588 #define MPI3_MAN6_PAGEVERSION (0x00) 589 590 /**** Defines for the Flags field ****/ 591 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 592 593 /***************************************************************************** 594 * Manufacturing Page 7 * 595 ****************************************************************************/ 596 typedef struct _MPI3_MAN7_RECEPTACLE_INFO 597 { 598 U32 Name[4]; /* 0x00 */ 599 U8 Location; /* 0x10 */ 600 U8 ConnectorType; /* 0x11 */ 601 U8 PEDClk; /* 0x12 */ 602 U8 ConnectorID; /* 0x13 */ 603 U32 Reserved14; /* 0x14 */ 604 } MPI3_MAN7_RECEPTACLE_INFO, MPI3_POINTER PTR_MPI3_MAN7_RECEPTACLE_INFO, 605 Mpi3Man7ReceptacleInfo_t, MPI3_POINTER pMpi3Man7ReceptacleInfo_t; 606 607 /**** Defines for Location field ****/ 608 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 609 #define MPI3_MAN7_LOCATION_INTERNAL (0x01) 610 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 611 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 612 #define MPI3_MAN7_LOCATION_HOST (0x04) 613 614 /**** Defines for ConnectorType - Use definitions from SES-4 ****/ 615 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) 616 617 /**** Defines for PEDClk field ****/ 618 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 619 #define MPI3_MAN7_PEDCLK_ROUTING_SHIFT (4) 620 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 621 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 622 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0F) 623 #define MPI3_MAN7_PEDCLK_ID_SHIFT (0) 624 625 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 626 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 627 #endif /* MPI3_MAN7_RECEPTACLE_INFO_MAX */ 628 629 typedef struct _MPI3_MAN_PAGE7 630 { 631 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 632 U32 Flags; /* 0x08 */ 633 U8 NumReceptacles; /* 0x0C */ 634 U8 Reserved0D[3]; /* 0x0D */ 635 U32 EnclosureName[4]; /* 0x10 */ 636 MPI3_MAN7_RECEPTACLE_INFO ReceptacleInfo[MPI3_MAN7_RECEPTACLE_INFO_MAX]; /* 0x20 */ /* variable length array */ 637 } MPI3_MAN_PAGE7, MPI3_POINTER PTR_MPI3_MAN_PAGE7, 638 Mpi3ManPage7_t, MPI3_POINTER pMpi3ManPage7_t; 639 640 /**** Defines for the PageVersion field ****/ 641 #define MPI3_MAN7_PAGEVERSION (0x00) 642 643 /**** Defines for Flags field ****/ 644 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 645 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_SHIFT (0) 646 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 647 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 648 649 650 /***************************************************************************** 651 * Manufacturing Page 8 * 652 ****************************************************************************/ 653 654 typedef struct _MPI3_MAN8_PHY_INFO 655 { 656 U8 ReceptacleID; /* 0x00 */ 657 U8 ConnectorLane; /* 0x01 */ 658 U16 Reserved02; /* 0x02 */ 659 U16 Slotx1; /* 0x04 */ 660 U16 Slotx2; /* 0x06 */ 661 U16 Slotx4; /* 0x08 */ 662 U16 Reserved0A; /* 0x0A */ 663 U32 Reserved0C; /* 0x0C */ 664 } MPI3_MAN8_PHY_INFO, MPI3_POINTER PTR_MPI3_MAN8_PHY_INFO, 665 Mpi3Man8PhyInfo_t, MPI3_POINTER pMpi3Man8PhyInfo_t; 666 667 /**** Defines for ReceptacleID field ****/ 668 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xFF) 669 670 /**** Defines for ConnectorLane field ****/ 671 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xFF) 672 673 #ifndef MPI3_MAN8_PHY_INFO_MAX 674 #define MPI3_MAN8_PHY_INFO_MAX (1) 675 #endif /* MPI3_MAN8_PHY_INFO_MAX */ 676 677 typedef struct _MPI3_MAN_PAGE8 678 { 679 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 680 U32 Reserved08; /* 0x08 */ 681 U8 NumPhys; /* 0x0C */ 682 U8 Reserved0D[3]; /* 0x0D */ 683 MPI3_MAN8_PHY_INFO PhyInfo[MPI3_MAN8_PHY_INFO_MAX]; /* 0x10 */ /* variable length array */ 684 } MPI3_MAN_PAGE8, MPI3_POINTER PTR_MPI3_MAN_PAGE8, 685 Mpi3ManPage8_t, MPI3_POINTER pMpi3ManPage8_t; 686 687 /**** Defines for the PageVersion field ****/ 688 #define MPI3_MAN8_PAGEVERSION (0x00) 689 690 /***************************************************************************** 691 * Manufacturing Page 9 * 692 ****************************************************************************/ 693 typedef struct _MPI3_MAN9_RSRC_ENTRY 694 { 695 U32 Maximum; /* 0x00 */ 696 U32 Decrement; /* 0x04 */ 697 U32 Minimum; /* 0x08 */ 698 U32 Actual; /* 0x0C */ 699 } MPI3_MAN9_RSRC_ENTRY, MPI3_POINTER PTR_MPI3_MAN9_RSRC_ENTRY, 700 Mpi3Man9RsrcEntry_t, MPI3_POINTER pMpi3Man9RsrcEntry_t; 701 702 typedef enum _MPI3_MAN9_RESOURCES 703 { 704 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 705 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 706 MPI3_MAN9_RSRC_RESERVED02 = 2, 707 MPI3_MAN9_RSRC_NVME = 3, 708 MPI3_MAN9_RSRC_INITIATORS = 4, 709 MPI3_MAN9_RSRC_VDS = 5, 710 MPI3_MAN9_RSRC_ENCLOSURES = 6, 711 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 712 MPI3_MAN9_RSRC_EXPANDERS = 8, 713 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 714 MPI3_MAN9_RSRC_RESERVED10 = 10, 715 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, 716 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, 717 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, 718 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, 719 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, 720 MPI3_MAN9_RSRC_NUM_RESOURCES 721 } MPI3_MAN9_RESOURCES; 722 723 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 724 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 725 726 #define MPI3_MAN9_MIN_TARGET_CMDS (0) 727 #define MPI3_MAN9_MAX_TARGET_CMDS (65535) 728 729 #define MPI3_MAN9_MIN_NVME_TARGETS (0) 730 /* Max NVMe Targets is product specific */ 731 732 #define MPI3_MAN9_MIN_INITIATORS (0) 733 /* Max Initiators is product specific */ 734 735 #define MPI3_MAN9_MIN_VDS (0) 736 /* Max VDs is product specific */ 737 738 #define MPI3_MAN9_MIN_ENCLOSURES (1) 739 #define MPI3_MAN9_MAX_ENCLOSURES (65535) 740 741 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 742 /* Max Enclosure Phys is product specific */ 743 744 #define MPI3_MAN9_MIN_EXPANDERS (0) 745 #define MPI3_MAN9_MAX_EXPANDERS (65535) 746 747 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 748 /* Max PCIe Switches is product specific */ 749 750 #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) 751 /* Max Host PD Drives is product specific */ 752 753 #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) 754 /* Max Advanced Host PD Drives is product specific */ 755 756 #define MPI3_MAN9_RAID_PD_DRIVES (0) 757 /* Max RAID PD Drives is product specific */ 758 759 #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) 760 /* Max Driver Diag Buffer is product specific */ 761 762 #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) 763 764 #define MPI3_MAN9_MIN_EXPANDERS (0) 765 #define MPI3_MAN9_MAX_EXPANDERS (65535) 766 767 768 typedef struct _MPI3_MAN_PAGE9 769 { 770 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 771 U8 NumResources; /* 0x08 */ 772 U8 Reserved09; /* 0x09 */ 773 U16 Reserved0A; /* 0x0A */ 774 U32 Reserved0C; /* 0x0C */ 775 U32 Reserved10; /* 0x10 */ 776 U32 Reserved14; /* 0x14 */ 777 U32 Reserved18; /* 0x18 */ 778 U32 Reserved1C; /* 0x1C */ 779 MPI3_MAN9_RSRC_ENTRY Resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; /* 0x20 */ 780 } MPI3_MAN_PAGE9, MPI3_POINTER PTR_MPI3_MAN_PAGE9, 781 Mpi3ManPage9_t, MPI3_POINTER pMpi3ManPage9_t; 782 783 /**** Defines for the PageVersion field ****/ 784 #define MPI3_MAN9_PAGEVERSION (0x00) 785 786 /***************************************************************************** 787 * Manufacturing Page 10 * 788 ****************************************************************************/ 789 typedef struct _MPI3_MAN10_ISTWI_CTRLR_ENTRY 790 { 791 U16 TargetAddress; /* 0x00 */ 792 U16 Flags; /* 0x02 */ 793 U8 SCLLowOverride; /* 0x04 */ 794 U8 SCLHighOverride; /* 0x05 */ 795 U16 Reserved06; /* 0x06 */ 796 } MPI3_MAN10_ISTWI_CTRLR_ENTRY, MPI3_POINTER PTR_MPI3_MAN10_ISTWI_CTRLR_ENTRY, 797 Mpi3Man10IstwiCtrlrEntry_t, MPI3_POINTER pMpi3Man10IstwiCtrlrEntry_t; 798 799 /**** Defines for the Flags field ****/ 800 801 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_MASK (0xC000) 802 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_SHIFT (14) 803 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_50_NS (0x0000) 804 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_10_NS (0x4000) 805 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_5_NS (0x8000) 806 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_0_NS (0xC000) 807 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_MASK (0x3000) 808 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_SHIFT (12) 809 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I2C (0x0000) 810 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I3C (0x1000) 811 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_AUTO (0x2000) 812 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_MASK (0x0E00) 813 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_SHIFT (9) 814 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_12_5_MHZ (0x0000) 815 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_8_MHZ (0x0200) 816 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_6_MHZ (0x0400) 817 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_4_MHZ (0x0600) 818 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800) 819 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000C) 820 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0) 821 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000) 822 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004) 823 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) 824 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) 825 826 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 827 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 828 #endif /* MPI3_MAN10_ISTWI_CTRLR_MAX */ 829 830 typedef struct _MPI3_MAN_PAGE10 831 { 832 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 833 U32 Reserved08; /* 0x08 */ 834 U8 NumISTWICtrl; /* 0x0C */ 835 U8 Reserved0D[3]; /* 0x0D */ 836 MPI3_MAN10_ISTWI_CTRLR_ENTRY ISTWIController[MPI3_MAN10_ISTWI_CTRLR_MAX]; /* 0x10 */ 837 } MPI3_MAN_PAGE10, MPI3_POINTER PTR_MPI3_MAN_PAGE10, 838 Mpi3ManPage10_t, MPI3_POINTER pMpi3ManPage10_t; 839 840 /**** Defines for the PageVersion field ****/ 841 #define MPI3_MAN10_PAGEVERSION (0x00) 842 843 /***************************************************************************** 844 * Manufacturing Page 11 * 845 ****************************************************************************/ 846 typedef struct _MPI3_MAN11_MUX_DEVICE_FORMAT 847 { 848 U8 MaxChannel; /* 0x00 */ 849 U8 Reserved01[3]; /* 0x01 */ 850 U32 Reserved04; /* 0x04 */ 851 } MPI3_MAN11_MUX_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MUX_DEVICE_FORMAT, 852 Mpi3Man11MuxDeviceFormat_t, MPI3_POINTER pMpi3Man11MuxDeviceFormat_t; 853 854 typedef struct _MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT 855 { 856 U8 Type; /* 0x00 */ 857 U8 Reserved01[3]; /* 0x01 */ 858 U8 TempChannel[4]; /* 0x04 */ 859 } MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, 860 Mpi3Man11TempSensorDeviceFormat_t, MPI3_POINTER pMpi3Man11TempSensorDeviceFormat_t; 861 862 /**** Defines for the Type field ****/ 863 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 864 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 865 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 866 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) 867 868 /**** Define for the TempChannel field ****/ 869 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xE0) 870 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) 871 /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ 872 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 873 874 875 typedef struct _MPI3_MAN11_SEEPROM_DEVICE_FORMAT 876 { 877 U8 Size; /* 0x00 */ 878 U8 PageWriteSize; /* 0x01 */ 879 U16 Reserved02; /* 0x02 */ 880 U32 Reserved04; /* 0x04 */ 881 } MPI3_MAN11_SEEPROM_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_SEEPROM_DEVICE_FORMAT, 882 Mpi3Man11SeepromDeviceFormat_t, MPI3_POINTER pMpi3Man11SeepromDeviceFormat_t; 883 884 /**** Defines for the Size field ****/ 885 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 886 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 887 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 888 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 889 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 890 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 891 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 892 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 893 894 typedef struct _MPI3_MAN11_DDR_SPD_DEVICE_FORMAT 895 { 896 U8 Channel; /* 0x00 */ 897 U8 Reserved01[3]; /* 0x01 */ 898 U32 Reserved04; /* 0x04 */ 899 } MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, 900 Mpi3Man11DdrSpdDeviceFormat_t, MPI3_POINTER pMpi3Man11DdrSpdDeviceFormat_t; 901 902 typedef struct _MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT 903 { 904 U8 Type; /* 0x00 */ 905 U8 ReceptacleID; /* 0x01 */ 906 U16 Reserved02; /* 0x02 */ 907 U32 Reserved04; /* 0x04 */ 908 } MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, 909 Mpi3Man11CableMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11CableMgmtDeviceFormat_t; 910 911 /**** Defines for the Type field ****/ 912 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 913 914 typedef struct _MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT 915 { 916 U16 Flags; /* 0x00 */ 917 U16 Reserved02; /* 0x02 */ 918 } MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, 919 Mpi3Man11BkplaneSpecUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecUBMFormat_t; 920 921 /**** Defines for the Flags field ****/ 922 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 923 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 924 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00F0) 925 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 926 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) 927 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 928 929 typedef struct _MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT 930 { 931 U16 Flags; /* 0x00 */ 932 U8 Reserved02; /* 0x02 */ 933 U8 Type; /* 0x03 */ 934 } MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, 935 Mpi3Man11BkplaneSpecNonUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecNonUBMFormat_t; 936 937 /**** Defines for the Flags field ****/ 938 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xF000) 939 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) 940 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_MASK (0x0600) 941 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SHIFT (9) 942 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_DEVICE_PRESENT (0x0000) 943 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 944 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SRIS (0x0400) 945 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00C0) 946 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_SHIFT (6) 947 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000) 948 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040) 949 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080) 950 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) 951 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_SHIFT (4) 952 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 953 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) 954 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) 955 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 956 957 /**** Defines for the Type field ****/ 958 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) 959 960 typedef union _MPI3_MAN11_BKPLANE_SPEC_FORMAT 961 { 962 MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT Ubm; 963 MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT NonUbm; 964 } MPI3_MAN11_BKPLANE_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_FORMAT, 965 Mpi3Man11BkplaneSpecFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecFormat_t; 966 967 typedef struct _MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT 968 { 969 U8 Type; /* 0x00 */ 970 U8 ReceptacleID; /* 0x01 */ 971 U8 ResetInfo; /* 0x02 */ 972 U8 Reserved03; /* 0x03 */ 973 MPI3_MAN11_BKPLANE_SPEC_FORMAT BackplaneMgmtSpecific; /* 0x04 */ 974 } MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, 975 Mpi3Man11BkplaneMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11BkplaneMgmtDeviceFormat_t; 976 977 /**** Defines for the Type field ****/ 978 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 979 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) 980 981 /**** Defines for the ResetInfo field ****/ 982 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xF0) 983 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) 984 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0F) 985 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) 986 987 typedef struct _MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT 988 { 989 U8 Type; /* 0x00 */ 990 U8 Reserved01[3]; /* 0x01 */ 991 U32 Reserved04; /* 0x04 */ 992 } MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, 993 Mpi3Man11GasGaugeDeviceFormat_t, MPI3_POINTER pMpi3Man11GasGaugeDeviceFormat_t; 994 995 /**** Defines for the Type field ****/ 996 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 997 998 typedef struct _MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT 999 { 1000 U32 Reserved00; /* 0x00 */ 1001 U32 Reserved04; /* 0x04 */ 1002 } MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, 1003 Mpi3Man11MgmtCtrlrDeviceFormat_t, MPI3_POINTER pMpi3Man11MgmtCtrlrDeviceFormat_t; 1004 1005 typedef struct _MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT 1006 { 1007 U8 Flags; /* 0x00 */ 1008 U8 Reserved01; /* 0x01 */ 1009 U8 MinFanSpeed; /* 0x02 */ 1010 U8 MaxFanSpeed; /* 0x03 */ 1011 U32 Reserved04; /* 0x04 */ 1012 } MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, 1013 Mpi3Man11BoardFanDeviceFormat_t, MPI3_POINTER pMpi3Man11BoardFanDeviceFormat_t; 1014 1015 /**** Defines for the Flags field ****/ 1016 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) 1017 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_SHIFT (0) 1018 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) 1019 1020 typedef union _MPI3_MAN11_DEVICE_SPECIFIC_FORMAT 1021 { 1022 MPI3_MAN11_MUX_DEVICE_FORMAT Mux; 1023 MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT TempSensor; 1024 MPI3_MAN11_SEEPROM_DEVICE_FORMAT Seeprom; 1025 MPI3_MAN11_DDR_SPD_DEVICE_FORMAT DdrSpd; 1026 MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT CableMgmt; 1027 MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT BkplaneMgmt; 1028 MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT GasGauge; 1029 MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT MgmtController; 1030 MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT BoardFan; 1031 U32 Words[2]; 1032 } MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, 1033 Mpi3Man11DeviceSpecificFormat_t, MPI3_POINTER pMpi3Man11DeviceSpecificFormat_t; 1034 1035 typedef struct _MPI3_MAN11_ISTWI_DEVICE_FORMAT 1036 { 1037 U8 DeviceType; /* 0x00 */ 1038 U8 Controller; /* 0x01 */ 1039 U8 Reserved02; /* 0x02 */ 1040 U8 Flags; /* 0x03 */ 1041 U16 DeviceAddress; /* 0x04 */ 1042 U8 MuxChannel; /* 0x06 */ 1043 U8 MuxIndex; /* 0x07 */ 1044 MPI3_MAN11_DEVICE_SPECIFIC_FORMAT DeviceSpecific; /* 0x08 */ 1045 } MPI3_MAN11_ISTWI_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_ISTWI_DEVICE_FORMAT, 1046 Mpi3Man11IstwiDeviceFormat_t, MPI3_POINTER pMpi3Man11IstwiDeviceFormat_t; 1047 1048 /**** Defines for the DeviceType field ****/ 1049 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 1050 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 1051 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 1052 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 1053 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 1054 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 1055 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 1056 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) 1057 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) 1058 1059 /**** Defines for the Flags field ****/ 1060 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 1061 1062 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 1063 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 1064 #endif /* MPI3_MAN11_ISTWI_DEVICE_MAX */ 1065 1066 typedef struct _MPI3_MAN_PAGE11 1067 { 1068 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1069 U32 Reserved08; /* 0x08 */ 1070 U8 NumISTWIDev; /* 0x0C */ 1071 U8 Reserved0D[3]; /* 0x0D */ 1072 MPI3_MAN11_ISTWI_DEVICE_FORMAT ISTWIDevice[MPI3_MAN11_ISTWI_DEVICE_MAX]; /* 0x10 */ 1073 } MPI3_MAN_PAGE11, MPI3_POINTER PTR_MPI3_MAN_PAGE11, 1074 Mpi3ManPage11_t, MPI3_POINTER pMpi3ManPage11_t; 1075 1076 /**** Defines for the PageVersion field ****/ 1077 #define MPI3_MAN11_PAGEVERSION (0x00) 1078 1079 1080 /***************************************************************************** 1081 * Manufacturing Page 12 * 1082 ****************************************************************************/ 1083 #ifndef MPI3_MAN12_NUM_SGPIO_MAX 1084 #define MPI3_MAN12_NUM_SGPIO_MAX (1) 1085 #endif /* MPI3_MAN12_NUM_SGPIO_MAX */ 1086 1087 typedef struct _MPI3_MAN12_SGPIO_INFO 1088 { 1089 U8 SlotCount; /* 0x00 */ 1090 U8 Reserved01[3]; /* 0x01 */ 1091 U32 Reserved04; /* 0x04 */ 1092 U8 PhyOrder[32]; /* 0x08 */ 1093 } MPI3_MAN12_SGPIO_INFO, MPI3_POINTER PTR_MPI3_MAN12_SGPIO_INFO, 1094 Mpi3Man12SGPIOInfo_t, MPI3_POINTER pMpi3Man12SGPIOInfo_t; 1095 1096 typedef struct _MPI3_MAN_PAGE12 1097 { 1098 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1099 U32 Flags; /* 0x08 */ 1100 U32 SClockFreq; /* 0x0C */ 1101 U32 ActivityModulation; /* 0x10 */ 1102 U8 NumSGPIO; /* 0x14 */ 1103 U8 Reserved15[3]; /* 0x15 */ 1104 U32 Reserved18; /* 0x18 */ 1105 U32 Reserved1C; /* 0x1C */ 1106 U32 Pattern[8]; /* 0x20 */ 1107 MPI3_MAN12_SGPIO_INFO SGPIOInfo[MPI3_MAN12_NUM_SGPIO_MAX]; /* 0x40 */ /* variable length */ 1108 } MPI3_MAN_PAGE12, MPI3_POINTER PTR_MPI3_MAN_PAGE12, 1109 Mpi3ManPage12_t, MPI3_POINTER pMpi3ManPage12_t; 1110 1111 /**** Defines for the PageVersion field ****/ 1112 #define MPI3_MAN12_PAGEVERSION (0x00) 1113 1114 /**** Defines for the Flags field ****/ 1115 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 1116 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 1117 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 1118 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 1119 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 1120 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_SHIFT (1) 1121 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 1122 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 1123 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 1124 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_SHIFT (0) 1125 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 1126 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 1127 1128 /**** Defines for the SClockFreq field ****/ 1129 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) /* 32 Hz min SIO Clk Freq */ 1130 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) /* 100 KHz max SIO Clk Freq */ 1131 1132 /**** Defines for the ActivityModulation field ****/ 1133 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000F000) 1134 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 1135 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000F00) 1136 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 1137 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000F0) 1138 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 1139 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000F) 1140 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 1141 1142 /*** Defines for the Pattern field ****/ 1143 #define MPI3_MAN12_PATTERN_RATE_MASK (0xE0000000) 1144 #define MPI3_MAN12_PATTERN_RATE_SHIFT (29) 1145 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 1146 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 1147 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 1148 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 1149 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 1150 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xA0000000) 1151 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xC0000000) 1152 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1F000000) 1153 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 1154 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00FFFFFF) 1155 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 1156 1157 1158 /***************************************************************************** 1159 * Manufacturing Page 13 * 1160 ****************************************************************************/ 1161 1162 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 1163 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 1164 #endif /* MPI3_MAN13_NUM_TRANSLATION_MAX */ 1165 1166 typedef struct _MPI3_MAN13_TRANSLATION_INFO 1167 { 1168 U32 SlotStatus; /* 0x00 */ 1169 U32 Mask; /* 0x04 */ 1170 U8 Activity; /* 0x08 */ 1171 U8 Locate; /* 0x09 */ 1172 U8 Error; /* 0x0A */ 1173 U8 Reserved0B; /* 0x0B */ 1174 } MPI3_MAN13_TRANSLATION_INFO, MPI3_POINTER PTR_MPI3_MAN13_TRANSLATION_INFO, 1175 Mpi3Man13TranslationInfo_t, MPI3_POINTER pMpi3Man13TranslationInfo_t; 1176 1177 /**** Defines for the SlotStatus field ****/ 1178 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 1179 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 1180 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 1181 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 1182 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 1183 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 1184 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 1185 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 1186 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 1187 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 1188 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 1189 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 1190 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 1191 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 1192 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 1193 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 1194 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 1195 1196 /**** Defines for the Mask field - use MPI3_MAN13_TRANSLATION_SLOTSTATUS_ defines ****/ 1197 1198 /**** Defines for the Activity, Locate, and Error fields ****/ 1199 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 1200 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 1201 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 1202 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 1203 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 1204 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 1205 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 1206 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 1207 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 1208 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 1209 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0A) 1210 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0B) 1211 1212 typedef struct _MPI3_MAN_PAGE13 1213 { 1214 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1215 U8 NumTrans; /* 0x08 */ 1216 U8 Reserved09[3]; /* 0x09 */ 1217 U32 Reserved0C; /* 0x0C */ 1218 MPI3_MAN13_TRANSLATION_INFO Translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; /* 0x10 */ /* variable length */ 1219 } MPI3_MAN_PAGE13, MPI3_POINTER PTR_MPI3_MAN_PAGE13, 1220 Mpi3ManPage13_t, MPI3_POINTER pMpi3ManPage13_t; 1221 1222 /**** Defines for the PageVersion field ****/ 1223 #define MPI3_MAN13_PAGEVERSION (0x00) 1224 1225 /***************************************************************************** 1226 * Manufacturing Page 14 * 1227 ****************************************************************************/ 1228 1229 typedef struct _MPI3_MAN_PAGE14 1230 { 1231 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1232 U32 Reserved08; /* 0x08 */ 1233 U8 NumSlotGroups; /* 0x0C */ 1234 U8 NumSlots; /* 0x0D */ 1235 U16 MaxCertChainLength; /* 0x0E */ 1236 U32 SealedSlots; /* 0x10 */ 1237 U32 PopulatedSlots; /* 0x14 */ 1238 U32 MgmtPTUpdatableSlots; /* 0x18 */ 1239 } MPI3_MAN_PAGE14, MPI3_POINTER PTR_MPI3_MAN_PAGE14, 1240 Mpi3ManPage14_t, MPI3_POINTER pMpi3ManPage14_t; 1241 1242 /**** Defines for the PageVersion field ****/ 1243 #define MPI3_MAN14_PAGEVERSION (0x00) 1244 1245 /**** Defines for the NumSlots field ****/ 1246 #define MPI3_MAN14_NUMSLOTS_MAX (32) 1247 1248 /***************************************************************************** 1249 * Manufacturing Page 15 * 1250 ****************************************************************************/ 1251 1252 #ifndef MPI3_MAN15_VERSION_RECORD_MAX 1253 #define MPI3_MAN15_VERSION_RECORD_MAX 1 1254 #endif /* MPI3_MAN15_VERSION_RECORD_MAX */ 1255 1256 typedef struct _MPI3_MAN15_VERSION_RECORD 1257 { 1258 U16 SPDMVersion; /* 0x00 */ 1259 U16 Reserved02; /* 0x02 */ 1260 } MPI3_MAN15_VERSION_RECORD, MPI3_POINTER PTR_MPI3_MAN15_VERSION_RECORD, 1261 Mpi3Man15VersionRecord_t, MPI3_POINTER pMpi3Man15VersionRecord_t; 1262 1263 typedef struct _MPI3_MAN_PAGE15 1264 { 1265 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1266 U8 NumVersionRecords; /* 0x08 */ 1267 U8 Reserved09[3]; /* 0x09 */ 1268 U32 Reserved0C; /* 0x0C */ 1269 MPI3_MAN15_VERSION_RECORD VersionRecord[MPI3_MAN15_VERSION_RECORD_MAX]; /* 0x10 */ 1270 } MPI3_MAN_PAGE15, MPI3_POINTER PTR_MPI3_MAN_PAGE15, 1271 Mpi3ManPage15_t, MPI3_POINTER pMpi3ManPage15_t; 1272 1273 /**** Defines for the PageVersion field ****/ 1274 #define MPI3_MAN15_PAGEVERSION (0x00) 1275 1276 /***************************************************************************** 1277 * Manufacturing Page 16 * 1278 ****************************************************************************/ 1279 1280 #ifndef MPI3_MAN16_CERT_ALGO_MAX 1281 #define MPI3_MAN16_CERT_ALGO_MAX 1 1282 #endif /* MPI3_MAN16_CERT_ALGO_MAX */ 1283 1284 typedef struct _MPI3_MAN16_CERTIFICATE_ALGORITHM 1285 { 1286 U8 SlotGroup; /* 0x00 */ 1287 U8 Reserved01[3]; /* 0x01 */ 1288 U32 BaseAsymAlgo; /* 0x04 */ 1289 U32 BaseHashAlgo; /* 0x08 */ 1290 U32 Reserved0C[3]; /* 0x0C */ 1291 } MPI3_MAN16_CERTIFICATE_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN16_CERTIFICATE_ALGORITHM, 1292 Mpi3Man16CertificateAlgorithm_t, MPI3_POINTER pMpi3Man16CertificateAlgorithm_t; 1293 1294 typedef struct _MPI3_MAN_PAGE16 1295 { 1296 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1297 U32 Reserved08; /* 0x08 */ 1298 U8 NumCertAlgos; /* 0x0C */ 1299 U8 Reserved0D[3]; /* 0x0D */ 1300 MPI3_MAN16_CERTIFICATE_ALGORITHM CertificateAlgorithm[MPI3_MAN16_CERT_ALGO_MAX]; /* 0x10 */ 1301 } MPI3_MAN_PAGE16, MPI3_POINTER PTR_MPI3_MAN_PAGE16, 1302 Mpi3ManPage16_t, MPI3_POINTER pMpi3ManPage16_t; 1303 1304 /**** Defines for the PageVersion field ****/ 1305 #define MPI3_MAN16_PAGEVERSION (0x00) 1306 1307 /***************************************************************************** 1308 * Manufacturing Page 17 * 1309 ****************************************************************************/ 1310 1311 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 1312 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 1313 #endif /* MPI3_MAN17_HASH_ALGORITHM_MAX */ 1314 1315 typedef struct _MPI3_MAN17_HASH_ALGORITHM 1316 { 1317 U8 MeasSpecification; /* 0x00 */ 1318 U8 Reserved01[3]; /* 0x01 */ 1319 U32 MeasurementHashAlgo; /* 0x04 */ 1320 U32 Reserved08[2]; /* 0x08 */ 1321 } MPI3_MAN17_HASH_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN17_HASH_ALGORITHM, 1322 Mpi3Man17HashAlgorithm_t, MPI3_POINTER pMpi3Man17HashAlgorithm_t; 1323 1324 typedef struct _MPI3_MAN_PAGE17 1325 { 1326 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1327 U32 Reserved08; /* 0x08 */ 1328 U8 NumHashAlgos; /* 0x0C */ 1329 U8 Reserved0D[3]; /* 0x0D */ 1330 MPI3_MAN17_HASH_ALGORITHM HashAlgorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; /* 0x10 */ 1331 } MPI3_MAN_PAGE17, MPI3_POINTER PTR_MPI3_MAN_PAGE17, 1332 Mpi3ManPage17_t, MPI3_POINTER pMpi3ManPage17_t; 1333 1334 /**** Defines for the PageVersion field ****/ 1335 #define MPI3_MAN17_PAGEVERSION (0x00) 1336 1337 /***************************************************************************** 1338 * Manufacturing Page 20 * 1339 ****************************************************************************/ 1340 1341 typedef struct _MPI3_MAN_PAGE20 1342 { 1343 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1344 U32 Reserved08; /* 0x08 */ 1345 U32 NonpremiumFeatures; /* 0x0C */ 1346 U8 AllowedPersonalities; /* 0x10 */ 1347 U8 Reserved11[3]; /* 0x11 */ 1348 } MPI3_MAN_PAGE20, MPI3_POINTER PTR_MPI3_MAN_PAGE20, 1349 Mpi3ManPage20_t, MPI3_POINTER pMpi3ManPage20_t; 1350 1351 /**** Defines for the PageVersion field ****/ 1352 #define MPI3_MAN20_PAGEVERSION (0x00) 1353 1354 /**** Defines for the AllowedPersonalities field ****/ 1355 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 1356 #define MPI3_MAN20_ALLOWEDPERSON_RAID_SHIFT (1) 1357 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 1358 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 1359 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 1360 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_SHIFT (0) 1361 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 1362 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 1363 1364 /**** Defines for the NonpremiumFeatures field ****/ 1365 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 1366 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_SHIFT (0) 1367 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 1368 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 1369 1370 /***************************************************************************** 1371 * Manufacturing Page 21 * 1372 ****************************************************************************/ 1373 1374 typedef struct _MPI3_MAN_PAGE21 1375 { 1376 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1377 U32 Reserved08; /* 0x08 */ 1378 U32 Flags; /* 0x0C */ 1379 } MPI3_MAN_PAGE21, MPI3_POINTER PTR_MPI3_MAN_PAGE21, 1380 Mpi3ManPage21_t, MPI3_POINTER pMpi3ManPage21_t; 1381 1382 /**** Defines for the PageVersion field ****/ 1383 #define MPI3_MAN21_PAGEVERSION (0x00) 1384 1385 /**** Defines for the Flags field ****/ 1386 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) 1387 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_SHIFT (5) 1388 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) 1389 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) 1390 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) 1391 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) 1392 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_SHIFT (3) 1393 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) 1394 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) 1395 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) 1396 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_SHIFT (0) 1397 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) 1398 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) 1399 1400 /***************************************************************************** 1401 * Manufacturing Page 22 * 1402 ****************************************************************************/ 1403 1404 typedef struct _MPI3_MAN_PAGE22 1405 { 1406 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1407 U32 Reserved08; /* 0x08 */ 1408 U16 NumEUI64; /* 0x0C */ 1409 U16 Reserved0E; /* 0x0E */ 1410 U64 BaseEUI64; /* 0x10 */ 1411 } MPI3_MAN_PAGE22, MPI3_POINTER PTR_MPI3_MAN_PAGE22, 1412 Mpi3ManPage22_t, MPI3_POINTER pMpi3ManPage22_t; 1413 1414 /**** Defines for the PageVersion field ****/ 1415 #define MPI3_MAN22_PAGEVERSION (0x00) 1416 1417 /***************************************************************************** 1418 * Manufacturing Pages 32-63 (ProductSpecific) * 1419 ****************************************************************************/ 1420 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX 1421 #define MPI3_MAN_PROD_SPECIFIC_MAX (1) 1422 #endif /* MPI3_MAN_PROD_SPECIFIC_MAX */ 1423 1424 typedef struct _MPI3_MAN_PAGE_PRODUCT_SPECIFIC 1425 { 1426 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1427 U32 ProductSpecificInfo[MPI3_MAN_PROD_SPECIFIC_MAX]; /* 0x08 */ /* variable length array */ 1428 } MPI3_MAN_PAGE_PRODUCT_SPECIFIC, MPI3_POINTER PTR_MPI3_MAN_PAGE_PRODUCT_SPECIFIC, 1429 Mpi3ManPageProductSpecific_t, MPI3_POINTER pMpi3ManPageProductSpecific_t; 1430 1431 /***************************************************************************** 1432 * IO Unit Configuration Pages * 1433 ****************************************************************************/ 1434 1435 /***************************************************************************** 1436 * IO Unit Page 0 * 1437 ****************************************************************************/ 1438 typedef struct _MPI3_IO_UNIT_PAGE0 1439 { 1440 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1441 U64 UniqueValue; /* 0x08 */ 1442 U32 NvdataVersionDefault; /* 0x10 */ 1443 U32 NvdataVersionPersistent; /* 0x14 */ 1444 } MPI3_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE0, 1445 Mpi3IOUnitPage0_t, MPI3_POINTER pMpi3IOUnitPage0_t; 1446 1447 /**** Defines for the PageVersion field ****/ 1448 #define MPI3_IOUNIT0_PAGEVERSION (0x00) 1449 1450 /***************************************************************************** 1451 * IO Unit Page 1 * 1452 ****************************************************************************/ 1453 typedef struct _MPI3_IO_UNIT_PAGE1 1454 { 1455 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1456 U32 Flags; /* 0x08 */ 1457 U8 DMDIoDelay; /* 0x0C */ 1458 U8 DMDReportPCIe; /* 0x0D */ 1459 U8 DMDReportSATA; /* 0x0E */ 1460 U8 DMDReportSAS; /* 0x0F */ 1461 } MPI3_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE1, 1462 Mpi3IOUnitPage1_t, MPI3_POINTER pMpi3IOUnitPage1_t; 1463 1464 /**** Defines for the PageVersion field ****/ 1465 #define MPI3_IOUNIT1_PAGEVERSION (0x00) 1466 1467 /**** Defines for the Flags field ****/ 1468 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 1469 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_SHIFT (4) 1470 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 1471 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 1472 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 1473 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 1474 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 1475 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 1476 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_SHIFT (0) 1477 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 1478 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 1479 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 1480 1481 /**** Defines for the DMDReport PCIe/SATA/SAS fields ****/ 1482 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) 1483 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_SHIFT (0) 1484 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 1485 1486 /***************************************************************************** 1487 * IO Unit Page 2 * 1488 ****************************************************************************/ 1489 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 1490 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 1491 #endif /* MPI3_IO_UNIT2_GPIO_VAL_MAX */ 1492 1493 typedef struct _MPI3_IO_UNIT_PAGE2 1494 { 1495 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1496 U8 GPIOCount; /* 0x08 */ 1497 U8 Reserved09[3]; /* 0x09 */ 1498 U16 GPIOVal[MPI3_IO_UNIT2_GPIO_VAL_MAX]; /* 0x0C */ 1499 } MPI3_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE2, 1500 Mpi3IOUnitPage2_t, MPI3_POINTER pMpi3IOUnitPage2_t; 1501 1502 /**** Defines for the PageVersion field ****/ 1503 #define MPI3_IOUNIT2_PAGEVERSION (0x00) 1504 1505 /**** Define for the GPIOVal field ****/ 1506 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xFFFC) 1507 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 1508 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 1509 #define MPI3_IOUNIT2_GPIO_SETTING_SHIFT (0) 1510 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 1511 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 1512 1513 /***************************************************************************** 1514 * IO Unit Page 3 * 1515 ****************************************************************************/ 1516 1517 typedef enum _MPI3_IOUNIT3_THRESHOLD 1518 { 1519 MPI3_IOUNIT3_THRESHOLD_WARNING = 0, 1520 MPI3_IOUNIT3_THRESHOLD_CRITICAL = 1, 1521 MPI3_IOUNIT3_THRESHOLD_FATAL = 2, 1522 MPI3_IOUNIT3_THRESHOLD_LOW = 3, 1523 MPI3_IOUNIT3_NUM_THRESHOLDS 1524 } MPI3_IOUNIT3_THRESHOLD; 1525 1526 typedef struct _MPI3_IO_UNIT3_SENSOR 1527 { 1528 U16 Flags; /* 0x00 */ 1529 U8 ThresholdMargin; /* 0x02 */ 1530 U8 Reserved03; /* 0x03 */ 1531 U16 Threshold[MPI3_IOUNIT3_NUM_THRESHOLDS]; /* 0x04 */ 1532 U32 Reserved0C; /* 0x0C */ 1533 U32 Reserved10; /* 0x10 */ 1534 U32 Reserved14; /* 0x14 */ 1535 } MPI3_IO_UNIT3_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT3_SENSOR, 1536 Mpi3IOUnit3Sensor_t, MPI3_POINTER pMpi3IOUnit3Sensor_t; 1537 1538 /**** Defines for the Flags field ****/ 1539 #define MPI3_IOUNIT3_SENSOR_FLAGS_LOW_THRESHOLD_VALID (0x0020) 1540 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) 1541 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) 1542 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) 1543 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) 1544 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) 1545 1546 #ifndef MPI3_IO_UNIT3_SENSOR_MAX 1547 #define MPI3_IO_UNIT3_SENSOR_MAX (1) 1548 #endif /* MPI3_IO_UNIT3_SENSOR_MAX */ 1549 1550 typedef struct _MPI3_IO_UNIT_PAGE3 1551 { 1552 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1553 U32 Reserved08; /* 0x08 */ 1554 U8 NumSensors; /* 0x0C */ 1555 U8 NominalPollInterval; /* 0x0D */ 1556 U8 WarningPollInterval; /* 0x0E */ 1557 U8 Reserved0F; /* 0x0F */ 1558 MPI3_IO_UNIT3_SENSOR Sensor[MPI3_IO_UNIT3_SENSOR_MAX]; /* 0x10 */ 1559 } MPI3_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE3, 1560 Mpi3IOUnitPage3_t, MPI3_POINTER pMpi3IOUnitPage3_t; 1561 1562 /**** Defines for the PageVersion field ****/ 1563 #define MPI3_IOUNIT3_PAGEVERSION (0x00) 1564 1565 1566 /***************************************************************************** 1567 * IO Unit Page 4 * 1568 ****************************************************************************/ 1569 typedef struct _MPI3_IO_UNIT4_SENSOR 1570 { 1571 U16 CurrentTemperature; /* 0x00 */ 1572 U16 Reserved02; /* 0x02 */ 1573 U8 Flags; /* 0x04 */ 1574 U8 Reserved05[3]; /* 0x05 */ 1575 U16 ISTWIIndex; /* 0x08 */ 1576 U8 Channel; /* 0x0A */ 1577 U8 Reserved0B; /* 0x0B */ 1578 U32 Reserved0C; /* 0x0C */ 1579 } MPI3_IO_UNIT4_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT4_SENSOR, 1580 Mpi3IOUnit4Sensor_t, MPI3_POINTER pMpi3IOUnit4Sensor_t; 1581 1582 /**** Defines for the Flags field ****/ 1583 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xE0) 1584 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) 1585 /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ 1586 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 1587 1588 1589 /**** Defines for the ISTWIIndex field ****/ 1590 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xFFFF) 1591 1592 /**** Defines for the Channel field ****/ 1593 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xFF) 1594 1595 #ifndef MPI3_IO_UNIT4_SENSOR_MAX 1596 #define MPI3_IO_UNIT4_SENSOR_MAX (1) 1597 #endif /* MPI3_IO_UNIT4_SENSOR_MAX */ 1598 1599 typedef struct _MPI3_IO_UNIT_PAGE4 1600 { 1601 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1602 U32 Reserved08; /* 0x08 */ 1603 U8 NumSensors; /* 0x0C */ 1604 U8 Reserved0D[3]; /* 0x0D */ 1605 MPI3_IO_UNIT4_SENSOR Sensor[MPI3_IO_UNIT4_SENSOR_MAX]; /* 0x10 */ 1606 } MPI3_IO_UNIT_PAGE4, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE4, 1607 Mpi3IOUnitPage4_t, MPI3_POINTER pMpi3IOUnitPage4_t; 1608 1609 /**** Defines for the PageVersion field ****/ 1610 #define MPI3_IOUNIT4_PAGEVERSION (0x00) 1611 1612 /***************************************************************************** 1613 * IO Unit Page 5 * 1614 ****************************************************************************/ 1615 typedef struct _MPI3_IO_UNIT5_SPINUP_GROUP 1616 { 1617 U8 MaxTargetSpinup; /* 0x00 */ 1618 U8 SpinupDelay; /* 0x01 */ 1619 U8 SpinupFlags; /* 0x02 */ 1620 U8 Reserved03; /* 0x03 */ 1621 } MPI3_IO_UNIT5_SPINUP_GROUP, MPI3_POINTER PTR_MPI3_IO_UNIT5_SPINUP_GROUP, 1622 Mpi3IOUnit5SpinupGroup_t, MPI3_POINTER pMpi3IOUnit5SpinupGroup_t; 1623 1624 /**** Defines for the SpinupFlags field ****/ 1625 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 1626 1627 #ifndef MPI3_IO_UNIT5_PHY_MAX 1628 #define MPI3_IO_UNIT5_PHY_MAX (4) 1629 #endif /* MPI3_IO_UNIT5_PHY_MAX */ 1630 1631 typedef struct _MPI3_IO_UNIT_PAGE5 1632 { 1633 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1634 MPI3_IO_UNIT5_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1635 U32 Reserved18; /* 0x18 */ 1636 U32 Reserved1C; /* 0x1C */ 1637 U16 DeviceShutdown; /* 0x20 */ 1638 U16 Reserved22; /* 0x22 */ 1639 U8 PCIeDeviceWaitTime; /* 0x24 */ 1640 U8 SATADeviceWaitTime; /* 0x25 */ 1641 U8 SpinupEnclDriveCount; /* 0x26 */ 1642 U8 SpinupEnclDelay; /* 0x27 */ 1643 U8 NumPhys; /* 0x28 */ 1644 U8 PEInitialSpinupDelay; /* 0x29 */ 1645 U8 TopologyStableTime; /* 0x2A */ 1646 U8 Flags; /* 0x2B */ 1647 U8 Phy[MPI3_IO_UNIT5_PHY_MAX]; /* 0x2C */ 1648 } MPI3_IO_UNIT_PAGE5, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE5, 1649 Mpi3IOUnitPage5_t, MPI3_POINTER pMpi3IOUnitPage5_t; 1650 1651 /**** Defines for the PageVersion field ****/ 1652 #define MPI3_IOUNIT5_PAGEVERSION (0x00) 1653 1654 /**** Defines for the DeviceShutdown field ****/ 1655 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) 1656 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) 1657 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) 1658 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) 1659 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) 1660 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) 1661 1662 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) 1663 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) 1664 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00C0) 1665 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) 1666 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) 1667 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) 1668 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000C) 1669 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) 1670 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) 1671 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0) 1672 1673 /**** Defines for the Flags field ****/ 1674 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0C) 1675 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_SHIFT (2) 1676 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00) 1677 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04) 1678 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08) 1679 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0C) 1680 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 1681 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 1682 1683 /**** Defines for the Phy field ****/ 1684 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 1685 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_SHIFT (0) 1686 1687 /***************************************************************************** 1688 * IO Unit Page 6 * 1689 ****************************************************************************/ 1690 typedef struct _MPI3_IO_UNIT_PAGE6 1691 { 1692 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1693 U32 BoardPowerRequirement; /* 0x08 */ 1694 U32 PCISlotPowerAllocation; /* 0x0C */ 1695 U8 Flags; /* 0x10 */ 1696 U8 Reserved11[3]; /* 0x11 */ 1697 } MPI3_IO_UNIT_PAGE6, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE6, 1698 Mpi3IOUnitPage6_t, MPI3_POINTER pMpi3IOUnitPage6_t; 1699 1700 /**** Defines for the PageVersion field ****/ 1701 #define MPI3_IOUNIT6_PAGEVERSION (0x00) 1702 1703 /**** Defines for the Flags field ****/ 1704 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 1705 1706 /***************************************************************************** 1707 * IO Unit Page 8 * 1708 ****************************************************************************/ 1709 1710 #ifndef MPI3_IOUNIT8_DIGEST_MAX 1711 #define MPI3_IOUNIT8_DIGEST_MAX (1) 1712 #endif /* MPI3_IOUNIT8_DIGEST_MAX */ 1713 1714 typedef union _MPI3_IOUNIT8_RAW_DIGEST 1715 { 1716 U32 Dword[16]; 1717 U16 Word[32]; 1718 U8 Byte[64]; 1719 } MPI3_IOUNIT8_RAW_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_RAW_DIGEST, 1720 Mpi3IOUnit8RawDigest_t, MPI3_POINTER pMpi3IOUnit8RawDigest_t; 1721 1722 typedef struct _MPI3_IOUNIT8_METADATA_DIGEST 1723 { 1724 U8 SlotStatus; /* 0x00 */ 1725 U8 Reserved01[3]; /* 0x01 */ 1726 U32 Reserved04[3]; /* 0x04 */ 1727 MPI3_IOUNIT8_RAW_DIGEST DigestData; /* 0x10 */ 1728 } MPI3_IOUNIT8_METADATA_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_METADATA_DIGEST, 1729 Mpi3IOUnit8MetadataDigest_t, MPI3_POINTER pMpi3IOUnit8MetadataDigest_t; 1730 1731 /**** Defines for the SlotStatus field ****/ 1732 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UNUSED (0x00) 1733 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UPDATE_PENDING (0x01) 1734 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_VALID (0x03) 1735 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_INVALID (0x07) 1736 1737 typedef union _MPI3_IOUNIT8_DIGEST 1738 { 1739 MPI3_IOUNIT8_RAW_DIGEST RawDigest[MPI3_IOUNIT8_DIGEST_MAX]; 1740 MPI3_IOUNIT8_METADATA_DIGEST MetadataDigest[MPI3_IOUNIT8_DIGEST_MAX]; 1741 } MPI3_IOUNIT8_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_DIGEST, 1742 Mpi3IOUnit8Digest_t, MPI3_POINTER pMpi3IOUnit8Digest_t; 1743 1744 typedef struct _MPI3_IO_UNIT_PAGE8 1745 { 1746 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1747 U8 SBMode; /* 0x08 */ 1748 U8 SBState; /* 0x09 */ 1749 U8 Flags; /* 0x0A */ 1750 U8 Reserved0A; /* 0x0B */ 1751 U8 NumSlots; /* 0x0C */ 1752 U8 SlotsAvailable; /* 0x0D */ 1753 U8 CurrentKeyEncryptionAlgo; /* 0x0E */ 1754 U8 KeyDigestHashAlgo; /* 0x0F */ 1755 MPI3_VERSION_UNION CurrentSvn; /* 0x10 */ 1756 U32 Reserved14; /* 0x14 */ 1757 U32 CurrentKey[128]; /* 0x18 */ 1758 MPI3_IOUNIT8_DIGEST Digest; /* 0x218 */ /* variable length */ 1759 } MPI3_IO_UNIT_PAGE8, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE8, 1760 Mpi3IOUnitPage8_t, MPI3_POINTER pMpi3IOUnitPage8_t; 1761 1762 /**** Defines for the PageVersion field ****/ 1763 #define MPI3_IOUNIT8_PAGEVERSION (0x00) 1764 1765 /**** Defines for the SBMode field ****/ 1766 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08) 1767 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 1768 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 1769 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 1770 1771 /**** Defines for the SBState field ****/ 1772 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) 1773 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 1774 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 1775 1776 /**** Defines for the Flags field ****/ 1777 #define MPI3_IOUNIT8_FLAGS_CURRENT_KEY_IOUNIT17 (0x08) 1778 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_MASK (0x07) 1779 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_SHIFT (0) 1780 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_RAW (0x00) 1781 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_DIGEST_WITH_METADATA (0x01) 1782 1783 /**** Use MPI3_ENCRYPTION_ALGORITHM_ defines (see mpi30_image.h) for the CurrentKeyEncryptionAlgo field ****/ 1784 /**** Use MPI3_HASH_ALGORITHM defines (see mpi30_image.h) for the KeyDigestHashAlgo field ****/ 1785 1786 /***************************************************************************** 1787 * IO Unit Page 9 * 1788 ****************************************************************************/ 1789 1790 typedef struct _MPI3_IO_UNIT_PAGE9 1791 { 1792 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1793 U32 Flags; /* 0x08 */ 1794 U16 FirstDevice; /* 0x0C */ 1795 U16 Reserved0E; /* 0x0E */ 1796 } MPI3_IO_UNIT_PAGE9, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE9, 1797 Mpi3IOUnitPage9_t, MPI3_POINTER pMpi3IOUnitPage9_t; 1798 1799 /**** Defines for the PageVersion field ****/ 1800 #define MPI3_IOUNIT9_PAGEVERSION (0x00) 1801 1802 /**** Defines for the Flags field ****/ 1803 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006) 1804 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1) 1805 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000) 1806 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002) 1807 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004) 1808 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001) 1809 1810 /**** Defines for the FirstDevice field ****/ 1811 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xFFFF) 1812 #define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xFFFE) 1813 1814 /***************************************************************************** 1815 * IO Unit Page 10 * 1816 ****************************************************************************/ 1817 1818 typedef struct _MPI3_IO_UNIT_PAGE10 1819 { 1820 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1821 U8 Flags; /* 0x08 */ 1822 U8 Reserved09[3]; /* 0x09 */ 1823 U32 SiliconID; /* 0x0C */ 1824 U8 FWVersionMinor; /* 0x10 */ 1825 U8 FWVersionMajor; /* 0x11 */ 1826 U8 HWVersionMinor; /* 0x12 */ 1827 U8 HWVersionMajor; /* 0x13 */ 1828 U8 PartNumber[16]; /* 0x14 */ 1829 } MPI3_IO_UNIT_PAGE10, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE10, 1830 Mpi3IOUnitPage10_t, MPI3_POINTER pMpi3IOUnitPage10_t; 1831 1832 /**** Defines for the PageVersion field ****/ 1833 #define MPI3_IOUNIT10_PAGEVERSION (0x00) 1834 1835 /**** Defines for the Flags field ****/ 1836 #define MPI3_IOUNIT10_FLAGS_VALID (0x01) 1837 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) 1838 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SHIFT (1) 1839 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) 1840 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) 1841 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) 1842 1843 /***************************************************************************** 1844 * IO Unit Page 11 * 1845 ****************************************************************************/ 1846 1847 #ifndef MPI3_IOUNIT11_PROFILE_MAX 1848 #define MPI3_IOUNIT11_PROFILE_MAX (1) 1849 #endif /* MPI3_IOUNIT11_PROFILE_MAX */ 1850 1851 typedef struct _MPI3_IOUNIT11_PROFILE 1852 { 1853 U8 ProfileIdentifier; /* 0x00 */ 1854 U8 Reserved01[3]; /* 0x01 */ 1855 U16 MaxVDs; /* 0x04 */ 1856 U16 MaxHostPDs; /* 0x06 */ 1857 U16 MaxAdvHostPDs; /* 0x08 */ 1858 U16 MaxRAIDPDs; /* 0x0A */ 1859 U16 MaxNVMe; /* 0x0C */ 1860 U16 MaxOutstandingRequests; /* 0x0E */ 1861 U16 SubsystemID; /* 0x10 */ 1862 U16 Reserved12; /* 0x12 */ 1863 U32 Reserved14[2]; /* 0x14 */ 1864 } MPI3_IOUNIT11_PROFILE, MPI3_POINTER PTR_MPI3_IOUNIT11_PROFILE, 1865 Mpi3IOUnit11Profile_t, MPI3_POINTER pMpi3IOUnit11Profile_t; 1866 1867 typedef struct _MPI3_IO_UNIT_PAGE11 1868 { 1869 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1870 U32 Reserved08; /* 0x08 */ 1871 U8 NumProfiles; /* 0x0C */ 1872 U8 CurrentProfileIdentifier; /* 0x0D */ 1873 U16 Reserved0E; /* 0x0E */ 1874 MPI3_IOUNIT11_PROFILE Profile[MPI3_IOUNIT11_PROFILE_MAX]; /* 0x10 */ /* variable length */ 1875 } MPI3_IO_UNIT_PAGE11, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE11, 1876 Mpi3IOUnitPage11_t, MPI3_POINTER pMpi3IOUnitPage11_t; 1877 1878 /**** Defines for the PageVersion field ****/ 1879 #define MPI3_IOUNIT11_PAGEVERSION (0x00) 1880 1881 /***************************************************************************** 1882 * IO Unit Page 12 * 1883 ****************************************************************************/ 1884 1885 #ifndef MPI3_IOUNIT12_BUCKET_MAX 1886 #define MPI3_IOUNIT12_BUCKET_MAX (1) 1887 #endif /* MPI3_IOUNIT12_BUCKET_MAX */ 1888 1889 typedef struct _MPI3_IOUNIT12_BUCKET 1890 { 1891 U8 CoalescingDepth; /* 0x00 */ 1892 U8 CoalescingTimeout; /* 0x01 */ 1893 U16 IOCountLowBoundary; /* 0x02 */ 1894 U32 Reserved04; /* 0x04 */ 1895 } MPI3_IOUNIT12_BUCKET, MPI3_POINTER PTR_MPI3_IOUNIT12_BUCKET, 1896 Mpi3IOUnit12Bucket_t, MPI3_POINTER pMpi3IOUnit12Bucket_t; 1897 1898 typedef struct _MPI3_IO_UNIT_PAGE12 1899 { 1900 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1901 U32 Flags; /* 0x08 */ 1902 U32 Reserved0C[4]; /* 0x0C */ 1903 U8 NumBuckets; /* 0x1C */ 1904 U8 Reserved1D[3]; /* 0x1D */ 1905 MPI3_IOUNIT12_BUCKET Bucket[MPI3_IOUNIT12_BUCKET_MAX]; /* 0x20 */ /* variable length */ 1906 } MPI3_IO_UNIT_PAGE12, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE12, 1907 Mpi3IOUnitPage12_t, MPI3_POINTER pMpi3IOUnitPage12_t; 1908 1909 /**** Defines for the PageVersion field ****/ 1910 #define MPI3_IOUNIT12_PAGEVERSION (0x00) 1911 1912 /**** Defines for the Flags field ****/ 1913 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300) 1914 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8) 1915 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000) 1916 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100) 1917 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) 1918 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) 1919 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) 1920 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_SHIFT (0) 1921 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) 1922 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) 1923 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) 1924 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003) 1925 1926 /***************************************************************************** 1927 * IO Unit Page 13 * 1928 ****************************************************************************/ 1929 1930 #ifndef MPI3_IOUNIT13_FUNC_MAX 1931 #define MPI3_IOUNIT13_FUNC_MAX (1) 1932 #endif /* MPI3_IOUNIT13_FUNC_MAX */ 1933 1934 typedef struct _MPI3_IOUNIT13_ALLOWED_FUNCTION 1935 { 1936 U16 SubFunction; /* 0x00 */ 1937 U8 FunctionCode; /* 0x02 */ 1938 U8 FunctionFlags; /* 0x03 */ 1939 } MPI3_IOUNIT13_ALLOWED_FUNCTION, MPI3_POINTER PTR_MPI3_IOUNIT13_ALLOWED_FUNCTION, 1940 Mpi3IOUnit13AllowedFunction_t, MPI3_POINTER pMpi3IOUnit13AllowedFunction_t; 1941 1942 /**** Defines for the FunctionFlags field ****/ 1943 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04) 1944 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02) 1945 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01) 1946 1947 typedef struct _MPI3_IO_UNIT_PAGE13 1948 { 1949 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1950 U16 Flags; /* 0x08 */ 1951 U16 Reserved0A; /* 0x0A */ 1952 U8 NumAllowedFunctions; /* 0x0C */ 1953 U8 Reserved0D[3]; /* 0x0D */ 1954 MPI3_IOUNIT13_ALLOWED_FUNCTION AllowedFunction[MPI3_IOUNIT13_FUNC_MAX]; /* 0x10 */ /* variable length */ 1955 } MPI3_IO_UNIT_PAGE13, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE13, 1956 Mpi3IOUnitPage13_t, MPI3_POINTER pMpi3IOUnitPage13_t; 1957 1958 /**** Defines for the PageVersion field ****/ 1959 #define MPI3_IOUNIT13_PAGEVERSION (0x00) 1960 1961 /**** Defines for the Flags field ****/ 1962 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002) 1963 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001) 1964 1965 /***************************************************************************** 1966 * IO Unit Page 14 * 1967 ****************************************************************************/ 1968 1969 #ifndef MPI3_IOUNIT14_MD_MAX 1970 #define MPI3_IOUNIT14_MD_MAX (1) 1971 #endif /* MPI3_IOUNIT14_MD_MAX */ 1972 1973 typedef struct _MPI3_IOUNIT14_PAGEMETADATA 1974 { 1975 U8 PageType; /* 0x00 */ 1976 U8 PageNumber; /* 0x01 */ 1977 U8 Reserved02; /* 0x02 */ 1978 U8 PageFlags; /* 0x03 */ 1979 } MPI3_IOUNIT14_PAGEMETADATA, MPI3_POINTER PTR_MPI3_IOUNIT14_PAGEMETADATA, 1980 Mpi3IOUnit14PageMetadata_t, MPI3_POINTER pMpi3IOUnit14PageMetadata_t; 1981 1982 /**** Defines for the PageFlags field ****/ 1983 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02) 1984 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01) 1985 1986 typedef struct _MPI3_IO_UNIT_PAGE14 1987 { 1988 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1989 U8 Flags; /* 0x08 */ 1990 U8 Reserved09[3]; /* 0x09 */ 1991 U8 NumPages; /* 0x0C */ 1992 U8 Reserved0D[3]; /* 0x0D */ 1993 MPI3_IOUNIT14_PAGEMETADATA PageMetadata[MPI3_IOUNIT14_MD_MAX]; /* 0x10 */ /* variable length */ 1994 } MPI3_IO_UNIT_PAGE14, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE14, 1995 Mpi3IOUnitPage14_t, MPI3_POINTER pMpi3IOUnitPage14_t; 1996 1997 /**** Defines for the PageVersion field ****/ 1998 #define MPI3_IOUNIT14_PAGEVERSION (0x00) 1999 2000 /**** Defines for the Flags field ****/ 2001 #define MPI3_IOUNIT14_FLAGS_READONLY (0x01) 2002 2003 /***************************************************************************** 2004 * IO Unit Page 15 * 2005 ****************************************************************************/ 2006 2007 #ifndef MPI3_IOUNIT15_PBD_MAX 2008 #define MPI3_IOUNIT15_PBD_MAX (1) 2009 #endif /* MPI3_IOUNIT15_PBD_MAX */ 2010 2011 typedef struct _MPI3_IO_UNIT_PAGE15 2012 { 2013 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2014 U8 Flags; /* 0x08 */ 2015 U8 Reserved09[3]; /* 0x09 */ 2016 U32 Reserved0C; /* 0x0C */ 2017 U8 PowerBudgetingCapability; /* 0x10 */ 2018 U8 Reserved11[3]; /* 0x11 */ 2019 U8 NumPowerBudgetData; /* 0x14 */ 2020 U8 Reserved15[3]; /* 0x15 */ 2021 U32 PowerBudgetData[MPI3_IOUNIT15_PBD_MAX]; /* 0x18 */ /* variable length */ 2022 } MPI3_IO_UNIT_PAGE15, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE15, 2023 Mpi3IOUnitPage15_t, MPI3_POINTER pMpi3IOUnitPage15_t; 2024 2025 /**** Defines for the PageVersion field ****/ 2026 #define MPI3_IOUNIT15_PAGEVERSION (0x00) 2027 2028 /**** Defines for the Flags field ****/ 2029 #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) 2030 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) 2031 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_SHIFT (0) 2032 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) 2033 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) 2034 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) 2035 2036 /**** Defines for the NumPowerBudgetData field ****/ 2037 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) 2038 2039 /***************************************************************************** 2040 * IO Unit Page 16 * 2041 ****************************************************************************/ 2042 2043 #ifndef MPI3_IOUNIT16_ERROR_MAX 2044 #define MPI3_IOUNIT16_ERROR_MAX (1) 2045 #endif /* MPI3_IOUNIT16_ERROR_MAX */ 2046 2047 typedef struct _MPI3_IOUNIT16_ERROR 2048 { 2049 U32 Offset; /* 0x00 */ 2050 U32 Reserved04; /* 0x04 */ 2051 U64 Count; /* 0x08 */ 2052 U64 Timestamp; /* 0x10 */ 2053 } MPI3_IOUNIT16_ERROR, MPI3_POINTER PTR_MPI3_IOUNIT16_ERROR, 2054 Mpi3IOUnit16Error_t, MPI3_POINTER pMpi3IOUnit16Error_t; 2055 2056 typedef struct _MPI3_IO_UNIT_PAGE16 2057 { 2058 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2059 U64 TotalErrorCount; /* 0x08 */ 2060 U32 Reserved10[3]; /* 0x10 */ 2061 U8 NumErrors; /* 0x1C */ 2062 U8 MaxErrorsTracked; /* 0x1D */ 2063 U16 Reserved1E; /* 0x1E */ 2064 MPI3_IOUNIT16_ERROR Error[MPI3_IOUNIT16_ERROR_MAX]; /* 0x20 */ /* variable length */ 2065 } MPI3_IO_UNIT_PAGE16, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE16, 2066 Mpi3IOUnitPage16_t, MPI3_POINTER pMpi3IOUnitPage16_t; 2067 2068 /**** Defines for the PageVersion field ****/ 2069 #define MPI3_IOUNIT16_PAGEVERSION (0x00) 2070 2071 /***************************************************************************** 2072 * IO Unit Page 17 * 2073 ****************************************************************************/ 2074 2075 #ifndef MPI3_IOUNIT17_CURRENTKEY_MAX 2076 #define MPI3_IOUNIT17_CURRENTKEY_MAX (1) 2077 #endif /* MPI3_IOUNIT17_CURRENTKEY_MAX */ 2078 2079 typedef struct _MPI3_IO_UNIT_PAGE17 2080 { 2081 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2082 U8 NumInstances; /* 0x08 */ 2083 U8 Instance; /* 0x09 */ 2084 U16 Reserved0A; /* 0x0A */ 2085 U32 Reserved0C[4]; /* 0x0C */ 2086 U16 KeyLength; /* 0x1C */ 2087 U8 EncryptionAlgorithm; /* 0x1E */ 2088 U8 Reserved1F; /* 0x1F */ 2089 U32 CurrentKey[MPI3_IOUNIT17_CURRENTKEY_MAX]; /* 0x20 */ /* variable length */ 2090 } MPI3_IO_UNIT_PAGE17, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE17, 2091 Mpi3IOUnitPage17_t, MPI3_POINTER pMpi3IOUnitPage17_t; 2092 2093 /**** Defines for the PageVersion field ****/ 2094 #define MPI3_IOUNIT17_PAGEVERSION (0x00) 2095 2096 /**** Use MPI3_ENCRYPTION_ALGORITHM_ defines (see mpi30_image.h) for the EncryptionAlgorithm field ****/ 2097 2098 /***************************************************************************** 2099 * IO Unit Page 18 * 2100 ****************************************************************************/ 2101 2102 typedef struct _MPI3_IO_UNIT_PAGE18 2103 { 2104 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2105 U8 Flags; /* 0x08 */ 2106 U8 PollInterval; /* 0x09 */ 2107 U16 Reserved0A; /* 0x0A */ 2108 U32 Reserved0C; /* 0x0C */ 2109 } MPI3_IO_UNIT_PAGE18, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE18, 2110 Mpi3IOUnitPage18_t, MPI3_POINTER pMpi3IOUnitPage18_t; 2111 2112 /**** Defines for the PageVersion field ****/ 2113 #define MPI3_IOUNIT18_PAGEVERSION (0x00) 2114 2115 /**** Defines for the Flags field ****/ 2116 #define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01) 2117 2118 /**** Defines for the PollInterval field ****/ 2119 #define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00) 2120 2121 /***************************************************************************** 2122 * IO Unit Page 19 * 2123 ****************************************************************************/ 2124 2125 #ifndef MPI3_IOUNIT19_DEVICE_MAX 2126 #define MPI3_IOUNIT19_DEVICE_MAX (1) 2127 #endif /* MPI3_IOUNIT19_DEVICE_MAX */ 2128 2129 typedef struct _MPI3_IOUNIT19_DEVICE_ 2130 { 2131 U16 Temperature; /* 0x00 */ 2132 U16 DevHandle; /* 0x02 */ 2133 U16 PersistentID; /* 0x04 */ 2134 U16 Reserved06; /* 0x06 */ 2135 } MPI3_IOUNIT19_DEVICE, MPI3_POINTER PTR_MPI3_IOUNIT19_DEVICE, 2136 Mpi3IOUnit19Device_t, MPI3_POINTER pMpi3IOUnit19Device_t; 2137 2138 /**** Defines for the Temperature field ****/ 2139 #define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000) 2140 2141 typedef struct _MPI3_IO_UNIT_PAGE19 2142 { 2143 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2144 U16 NumDevices; /* 0x08 */ 2145 U16 Reserved0A; /* 0x0A */ 2146 U32 Reserved0C; /* 0x0C */ 2147 MPI3_IOUNIT19_DEVICE Device[MPI3_IOUNIT19_DEVICE_MAX]; /* 0x10 */ 2148 } MPI3_IO_UNIT_PAGE19, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE19, 2149 Mpi3IOUnitPage19_t, MPI3_POINTER pMpi3IOUnitPage19_t; 2150 2151 /**** Defines for the PageVersion field ****/ 2152 #define MPI3_IOUNIT19_PAGEVERSION (0x00) 2153 2154 2155 /***************************************************************************** 2156 * IOC Configuration Pages * 2157 ****************************************************************************/ 2158 2159 /***************************************************************************** 2160 * IOC Page 0 * 2161 ****************************************************************************/ 2162 typedef struct _MPI3_IOC_PAGE0 2163 { 2164 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2165 U32 Reserved08; /* 0x08 */ 2166 U16 VendorID; /* 0x0C */ 2167 U16 DeviceID; /* 0x0E */ 2168 U8 RevisionID; /* 0x10 */ 2169 U8 Reserved11[3]; /* 0x11 */ 2170 U32 ClassCode; /* 0x14 */ 2171 U16 SubsystemVendorID; /* 0x18 */ 2172 U16 SubsystemID; /* 0x1A */ 2173 } MPI3_IOC_PAGE0, MPI3_POINTER PTR_MPI3_IOC_PAGE0, 2174 Mpi3IOCPage0_t, MPI3_POINTER pMpi3IOCPage0_t; 2175 2176 /**** Defines for the PageVersion field ****/ 2177 #define MPI3_IOC0_PAGEVERSION (0x00) 2178 2179 /***************************************************************************** 2180 * IOC Page 1 * 2181 ****************************************************************************/ 2182 typedef struct _MPI3_IOC_PAGE1 2183 { 2184 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2185 U32 CoalescingTimeout; /* 0x08 */ 2186 U8 CoalescingDepth; /* 0x0C */ 2187 U8 Obsolete; /* 0x0D */ 2188 U16 Reserved0E; /* 0x0E */ 2189 } MPI3_IOC_PAGE1, MPI3_POINTER PTR_MPI3_IOC_PAGE1, 2190 Mpi3IOCPage1_t, MPI3_POINTER pMpi3IOCPage1_t; 2191 2192 /**** Defines for the PageVersion field ****/ 2193 #define MPI3_IOC1_PAGEVERSION (0x00) 2194 2195 /***************************************************************************** 2196 * IOC Page 2 * 2197 ****************************************************************************/ 2198 #ifndef MPI3_IOC2_EVENTMASK_WORDS 2199 #define MPI3_IOC2_EVENTMASK_WORDS (4) 2200 #endif /* MPI3_IOC2_EVENTMASK_WORDS */ 2201 2202 typedef struct _MPI3_IOC_PAGE2 2203 { 2204 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2205 U32 Reserved08; /* 0x08 */ 2206 U16 SASBroadcastPrimitiveMasks; /* 0x0C */ 2207 U16 SASNotifyPrimitiveMasks; /* 0x0E */ 2208 U32 EventMasks[MPI3_IOC2_EVENTMASK_WORDS]; /* 0x10 */ 2209 } MPI3_IOC_PAGE2, MPI3_POINTER PTR_MPI3_IOC_PAGE2, 2210 Mpi3IOCPage2_t, MPI3_POINTER pMpi3IOCPage2_t; 2211 2212 /**** Defines for the PageVersion field ****/ 2213 #define MPI3_IOC2_PAGEVERSION (0x00) 2214 2215 2216 /***************************************************************************** 2217 * Driver Configuration Pages * 2218 ****************************************************************************/ 2219 2220 /**** Defines for the Flags field in Driver Pages 10, 20, and 30 ****/ 2221 /**** NOT used in Driver Page 1 Flags field ****/ 2222 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) 2223 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) 2224 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) 2225 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) 2226 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) 2227 2228 typedef struct _MPI3_ALLOWED_CMD_SCSI 2229 { 2230 U16 ServiceAction; /* 0x00 */ 2231 U8 OperationCode; /* 0x02 */ 2232 U8 CommandFlags; /* 0x03 */ 2233 } MPI3_ALLOWED_CMD_SCSI, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_SCSI, 2234 Mpi3AllowedCmdScsi_t, MPI3_POINTER pMpi3AllowedCmdScsi_t; 2235 2236 typedef struct _MPI3_ALLOWED_CMD_ATA 2237 { 2238 U8 Subcommand; /* 0x00 */ 2239 U8 Reserved01; /* 0x01 */ 2240 U8 Command; /* 0x02 */ 2241 U8 CommandFlags; /* 0x03 */ 2242 } MPI3_ALLOWED_CMD_ATA, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_ATA, 2243 Mpi3AllowedCmdAta_t, MPI3_POINTER pMpi3AllowedCmdAta_t; 2244 2245 typedef struct _MPI3_ALLOWED_CMD_NVME 2246 { 2247 U8 Reserved00; /* 0x00 */ 2248 U8 NVMeCmdFlags; /* 0x01 */ 2249 U8 OpCode; /* 0x02 */ 2250 U8 CommandFlags; /* 0x03 */ 2251 } MPI3_ALLOWED_CMD_NVME, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_NVME, 2252 Mpi3AllowedCmdNvme_t, MPI3_POINTER pMpi3AllowedCmdNvme_t; 2253 2254 /**** Defines for the NVMeCmdFlags field ****/ 2255 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) 2256 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_SHIFT (7) 2257 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) 2258 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) 2259 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3F) 2260 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_SHIFT (0) 2261 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) 2262 2263 typedef union _MPI3_ALLOWED_CMD 2264 { 2265 MPI3_ALLOWED_CMD_SCSI Scsi; 2266 MPI3_ALLOWED_CMD_ATA Ata; 2267 MPI3_ALLOWED_CMD_NVME NVMe; 2268 } MPI3_ALLOWED_CMD, MPI3_POINTER PTR_MPI3_ALLOWED_CMD, 2269 Mpi3AllowedCmd_t, MPI3_POINTER pMpi3AllowedCmd_t; 2270 2271 /**** Defines for the CommandFlags field ****/ 2272 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) 2273 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) 2274 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) 2275 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) 2276 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) 2277 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) 2278 2279 2280 #ifndef MPI3_ALLOWED_CMDS_MAX 2281 #define MPI3_ALLOWED_CMDS_MAX (1) 2282 #endif /* MPI3_ALLOWED_CMDS_MAX */ 2283 2284 /***************************************************************************** 2285 * Driver Page 0 * 2286 ****************************************************************************/ 2287 typedef struct _MPI3_DRIVER_PAGE0 2288 { 2289 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2290 U32 BSDOptions; /* 0x08 */ 2291 U8 SSUTimeout; /* 0x0C */ 2292 U8 IOTimeout; /* 0x0D */ 2293 U8 TURRetries; /* 0x0E */ 2294 U8 TURInterval; /* 0x0F */ 2295 U8 Reserved10; /* 0x10 */ 2296 U8 SecurityKeyTimeout; /* 0x11 */ 2297 U16 FirstDevice; /* 0x12 */ 2298 U32 Reserved14; /* 0x14 */ 2299 U32 Reserved18; /* 0x18 */ 2300 } MPI3_DRIVER_PAGE0, MPI3_POINTER PTR_MPI3_DRIVER_PAGE0, 2301 Mpi3DriverPage0_t, MPI3_POINTER pMpi3DriverPage0_t; 2302 2303 /**** Defines for the PageVersion field ****/ 2304 #define MPI3_DRIVER0_PAGEVERSION (0x00) 2305 2306 /**** Defines for the BSDOptions field ****/ 2307 #define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020) 2308 #define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010) 2309 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) 2310 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 2311 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) 2312 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_SHIFT (0) 2313 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 2314 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 2315 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) 2316 2317 /**** Defines for the FirstDevice field ****/ 2318 #define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000) 2319 #define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xFFFF) 2320 2321 /***************************************************************************** 2322 * Driver Page 1 * 2323 ****************************************************************************/ 2324 typedef struct _MPI3_DRIVER_PAGE1 2325 { 2326 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2327 U32 Flags; /* 0x08 */ 2328 U8 TimeStampUpdate; /* 0x0C */ 2329 U8 Reserved0D[3]; /* 0x0D */ 2330 U16 HostDiagTraceMaxSize; /* 0x10 */ 2331 U16 HostDiagTraceMinSize; /* 0x12 */ 2332 U16 HostDiagTraceDecrementSize; /* 0x14 */ 2333 U16 Reserved16; /* 0x16 */ 2334 U16 HostDiagFwMaxSize; /* 0x18 */ 2335 U16 HostDiagFwMinSize; /* 0x1A */ 2336 U16 HostDiagFwDecrementSize; /* 0x1C */ 2337 U16 Reserved1E; /* 0x1E */ 2338 U16 HostDiagDriverMaxSize; /* 0x20 */ 2339 U16 HostDiagDriverMinSize; /* 0x22 */ 2340 U16 HostDiagDriverDecrementSize; /* 0x24 */ 2341 U16 Reserved26; /* 0x26 */ 2342 } MPI3_DRIVER_PAGE1, MPI3_POINTER PTR_MPI3_DRIVER_PAGE1, 2343 Mpi3DriverPage1_t, MPI3_POINTER pMpi3DriverPage1_t; 2344 2345 /**** Defines for the PageVersion field ****/ 2346 #define MPI3_DRIVER1_PAGEVERSION (0x00) 2347 2348 /***************************************************************************** 2349 * Driver Page 2 * 2350 ****************************************************************************/ 2351 #ifndef MPI3_DRIVER2_TRIGGER_MAX 2352 #define MPI3_DRIVER2_TRIGGER_MAX (1) 2353 #endif /* MPI3_DRIVER2_TRIGGER_MAX */ 2354 2355 typedef struct _MPI3_DRIVER2_TRIGGER_EVENT 2356 { 2357 U8 Type; /* 0x00 */ 2358 U8 Flags; /* 0x01 */ 2359 U8 Reserved02; /* 0x02 */ 2360 U8 Event; /* 0x03 */ 2361 U32 Reserved04[3]; /* 0x04 */ 2362 } MPI3_DRIVER2_TRIGGER_EVENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_EVENT, 2363 Mpi3Driver2TriggerEvent_t, MPI3_POINTER pMpi3Driver2TriggerEvent_t; 2364 2365 typedef struct _MPI3_DRIVER2_TRIGGER_SCSI_SENSE 2366 { 2367 U8 Type; /* 0x00 */ 2368 U8 Flags; /* 0x01 */ 2369 U16 Reserved02; /* 0x02 */ 2370 U8 ASCQ; /* 0x04 */ 2371 U8 ASC; /* 0x05 */ 2372 U8 SenseKey; /* 0x06 */ 2373 U8 Reserved07; /* 0x07 */ 2374 U32 Reserved08[2]; /* 0x08 */ 2375 } MPI3_DRIVER2_TRIGGER_SCSI_SENSE, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_SCSI_SENSE, 2376 Mpi3Driver2TriggerScsiSense_t, MPI3_POINTER pMpi3Driver2TriggerScsiSense_t; 2377 2378 /**** Defines for the ASCQ field ****/ 2379 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xFF) 2380 2381 /**** Defines for the ASC field ****/ 2382 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xFF) 2383 2384 /**** Defines for the SenseKey field ****/ 2385 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xFF) 2386 2387 typedef struct _MPI3_DRIVER2_TRIGGER_REPLY 2388 { 2389 U8 Type; /* 0x00 */ 2390 U8 Flags; /* 0x01 */ 2391 U16 IOCStatus; /* 0x02 */ 2392 U32 IOCLogInfo; /* 0x04 */ 2393 U32 IOCLogInfoMask; /* 0x08 */ 2394 U32 Reserved0C; /* 0x0C */ 2395 } MPI3_DRIVER2_TRIGGER_REPLY, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_REPLY, 2396 Mpi3Driver2TriggerReply_t, MPI3_POINTER pMpi3Driver2TriggerReply_t; 2397 2398 /**** Defines for the IOCStatus field ****/ 2399 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xFFFF) 2400 2401 typedef union _MPI3_DRIVER2_TRIGGER_ELEMENT 2402 { 2403 MPI3_DRIVER2_TRIGGER_EVENT Event; 2404 MPI3_DRIVER2_TRIGGER_SCSI_SENSE ScsiSense; 2405 MPI3_DRIVER2_TRIGGER_REPLY Reply; 2406 } MPI3_DRIVER2_TRIGGER_ELEMENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_ELEMENT, 2407 Mpi3Driver2TriggerElement_t, MPI3_POINTER pMpi3Driver2TriggerElement_t; 2408 2409 /**** Defines for the Type field ****/ 2410 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) 2411 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) 2412 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) 2413 2414 /**** Defines for the Flags field ****/ 2415 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) 2416 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) 2417 2418 typedef struct _MPI3_DRIVER_PAGE2 2419 { 2420 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2421 U64 GlobalTrigger; /* 0x08 */ 2422 U32 Reserved10[3]; /* 0x10 */ 2423 U8 NumTriggers; /* 0x1C */ 2424 U8 Reserved1D[3]; /* 0x1D */ 2425 MPI3_DRIVER2_TRIGGER_ELEMENT Trigger[MPI3_DRIVER2_TRIGGER_MAX]; /* 0x20 */ /* variable length */ 2426 } MPI3_DRIVER_PAGE2, MPI3_POINTER PTR_MPI3_DRIVER_PAGE2, 2427 Mpi3DriverPage2_t, MPI3_POINTER pMpi3DriverPage2_t; 2428 2429 /**** Defines for the PageVersion field ****/ 2430 #define MPI3_DRIVER2_PAGEVERSION (0x00) 2431 2432 /**** Defines for the GlobalTrigger field ****/ 2433 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) 2434 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) 2435 #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL) 2436 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL) 2437 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL) 2438 #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) 2439 #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) 2440 2441 /***************************************************************************** 2442 * Driver Page 10 * 2443 ****************************************************************************/ 2444 2445 typedef struct _MPI3_DRIVER_PAGE10 2446 { 2447 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2448 U16 Flags; /* 0x08 */ 2449 U16 Reserved0A; /* 0x0A */ 2450 U8 NumAllowedCommands; /* 0x0C */ 2451 U8 Reserved0D[3]; /* 0x0D */ 2452 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2453 } MPI3_DRIVER_PAGE10, MPI3_POINTER PTR_MPI3_DRIVER_PAGE10, 2454 Mpi3DriverPage10_t, MPI3_POINTER pMpi3DriverPage10_t; 2455 2456 /**** Defines for the PageVersion field ****/ 2457 #define MPI3_DRIVER10_PAGEVERSION (0x00) 2458 2459 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2460 2461 /***************************************************************************** 2462 * Driver Page 20 * 2463 ****************************************************************************/ 2464 2465 typedef struct _MPI3_DRIVER_PAGE20 2466 { 2467 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2468 U16 Flags; /* 0x08 */ 2469 U16 Reserved0A; /* 0x0A */ 2470 U8 NumAllowedCommands; /* 0x0C */ 2471 U8 Reserved0D[3]; /* 0x0D */ 2472 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2473 } MPI3_DRIVER_PAGE20, MPI3_POINTER PTR_MPI3_DRIVER_PAGE20, 2474 Mpi3DriverPage20_t, MPI3_POINTER pMpi3DriverPage20_t; 2475 2476 /**** Defines for the PageVersion field ****/ 2477 #define MPI3_DRIVER20_PAGEVERSION (0x00) 2478 2479 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2480 2481 /***************************************************************************** 2482 * Driver Page 30 * 2483 ****************************************************************************/ 2484 2485 typedef struct _MPI3_DRIVER_PAGE30 2486 { 2487 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2488 U16 Flags; /* 0x08 */ 2489 U16 Reserved0A; /* 0x0A */ 2490 U8 NumAllowedCommands; /* 0x0C */ 2491 U8 Reserved0D[3]; /* 0x0D */ 2492 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2493 } MPI3_DRIVER_PAGE30, MPI3_POINTER PTR_MPI3_DRIVER_PAGE30, 2494 Mpi3DriverPage30_t, MPI3_POINTER pMpi3DriverPage30_t; 2495 2496 /**** Defines for the PageVersion field ****/ 2497 #define MPI3_DRIVER30_PAGEVERSION (0x00) 2498 2499 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2500 2501 /***************************************************************************** 2502 * Security Configuration Pages * 2503 ****************************************************************************/ 2504 2505 typedef union _MPI3_SECURITY_MAC 2506 { 2507 U32 Dword[16]; 2508 U16 Word[32]; 2509 U8 Byte[64]; 2510 } MPI3_SECURITY_MAC, MPI3_POINTER PTR_MPI3_SECURITY_MAC, 2511 Mpi3SecurityMAC_t, MPI3_POINTER pMpi3SecurityMAC_t; 2512 2513 typedef union _MPI3_SECURITY_NONCE 2514 { 2515 U32 Dword[16]; 2516 U16 Word[32]; 2517 U8 Byte[64]; 2518 } MPI3_SECURITY_NONCE, MPI3_POINTER PTR_MPI3_SECURITY_NONCE, 2519 Mpi3SecurityNonce_t, MPI3_POINTER pMpi3SecurityNonce_t; 2520 2521 /***************************************************************************** 2522 * Security Page 0 * 2523 ****************************************************************************/ 2524 2525 typedef union _MPI3_SECURITY0_CERT_CHAIN 2526 { 2527 U32 Dword[1024]; 2528 U16 Word[2048]; 2529 U8 Byte[4096]; 2530 } MPI3_SECURITY0_CERT_CHAIN, MPI3_POINTER PTR_MPI3_SECURITY0_CERT_CHAIN, 2531 Mpi3Security0CertChain_t, MPI3_POINTER pMpi3Security0CertChain_t; 2532 2533 typedef struct _MPI3_SECURITY_PAGE0 2534 { 2535 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2536 U8 SlotNumGroup; /* 0x08 */ 2537 U8 SlotNum; /* 0x09 */ 2538 U16 CertChainLength; /* 0x0A */ 2539 U8 CertChainFlags; /* 0x0C */ 2540 U8 Reserved0D[3]; /* 0x0D */ 2541 U32 BaseAsymAlgo; /* 0x10 */ 2542 U32 BaseHashAlgo; /* 0x14 */ 2543 U32 Reserved18[4]; /* 0x18 */ 2544 MPI3_SECURITY_MAC Mac; /* 0x28 */ 2545 MPI3_SECURITY_NONCE Nonce; /* 0x68 */ 2546 MPI3_SECURITY0_CERT_CHAIN CertificateChain; /* 0xA8 */ 2547 } MPI3_SECURITY_PAGE0, MPI3_POINTER PTR_MPI3_SECURITY_PAGE0, 2548 Mpi3SecurityPage0_t, MPI3_POINTER pMpi3SecurityPage0_t; 2549 2550 /**** Defines for the PageVersion field ****/ 2551 #define MPI3_SECURITY0_PAGEVERSION (0x00) 2552 2553 /**** Defines for the CertChainFlags field ****/ 2554 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0E) 2555 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SHIFT (1) 2556 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 2557 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 2558 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 2559 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 2560 2561 /***************************************************************************** 2562 * Security Page 1 * 2563 ****************************************************************************/ 2564 2565 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX 2566 #define MPI3_SECURITY1_KEY_RECORD_MAX 1 2567 #endif /* MPI3_SECURITY1_KEY_RECORD_MAX */ 2568 2569 #ifndef MPI3_SECURITY1_PAD_MAX 2570 #define MPI3_SECURITY1_PAD_MAX 4 2571 #endif /* MPI3_SECURITY1_PAD_MAX */ 2572 2573 typedef union _MPI3_SECURITY1_KEY_DATA 2574 { 2575 U32 Dword[128]; 2576 U16 Word[256]; 2577 U8 Byte[512]; 2578 } MPI3_SECURITY1_KEY_DATA, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_DATA, 2579 Mpi3Security1KeyData_t, MPI3_POINTER pMpi3Security1KeyData_t; 2580 2581 typedef struct _MPI3_SECURITY1_KEY_RECORD 2582 { 2583 U8 Flags; /* 0x00 */ 2584 U8 Consumer; /* 0x01 */ 2585 U16 KeyDataSize; /* 0x02 */ 2586 U32 AdditionalKeyData; /* 0x04 */ 2587 U32 Reserved08[2]; /* 0x08 */ 2588 MPI3_SECURITY1_KEY_DATA KeyData; /* 0x10 */ 2589 } MPI3_SECURITY1_KEY_RECORD, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_RECORD, 2590 Mpi3Security1KeyRecord_t, MPI3_POINTER pMpi3Security1KeyRecord_t; 2591 2592 /**** Defines for the Flags field ****/ 2593 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1F) 2594 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_SHIFT (0) 2595 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 2596 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 2597 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 2598 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 2599 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 2600 2601 /**** Defines for the Consumer field ****/ 2602 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 2603 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 2604 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 2605 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) 2606 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 2607 2608 typedef struct _MPI3_SECURITY_PAGE1 2609 { 2610 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2611 U32 Reserved08[2]; /* 0x08 */ 2612 MPI3_SECURITY_MAC Mac; /* 0x10 */ 2613 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ 2614 U8 NumKeys; /* 0x90 */ 2615 U8 Reserved91[3]; /* 0x91 */ 2616 U32 Reserved94[3]; /* 0x94 */ 2617 MPI3_SECURITY1_KEY_RECORD KeyRecord[MPI3_SECURITY1_KEY_RECORD_MAX]; /* 0xA0 */ 2618 U8 Pad[MPI3_SECURITY1_PAD_MAX]; /* ?? */ 2619 } MPI3_SECURITY_PAGE1, MPI3_POINTER PTR_MPI3_SECURITY_PAGE1, 2620 Mpi3SecurityPage1_t, MPI3_POINTER pMpi3SecurityPage1_t; 2621 2622 /**** Defines for the PageVersion field ****/ 2623 #define MPI3_SECURITY1_PAGEVERSION (0x00) 2624 2625 2626 /***************************************************************************** 2627 * Security Page 2 * 2628 ****************************************************************************/ 2629 2630 #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX 2631 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 2632 #endif /* MPI3_SECURITY2_TRUSTED_ROOT_MAX */ 2633 2634 #ifndef MPI3_SECURITY2_ROOT_LEN 2635 #define MPI3_SECURITY2_ROOT_LEN 4 2636 #endif /* MPI3_SECURITY2_ROOT_LEN */ 2637 2638 typedef struct _MPI3_SECURITY2_TRUSTED_ROOT 2639 { 2640 U8 Level; /* 0x00 */ 2641 U8 HashAlgorithm; /* 0x01 */ 2642 U16 TrustedRootFlags; /* 0x02 */ 2643 U32 Reserved04[3]; /* 0x04 */ 2644 U8 Root[MPI3_SECURITY2_ROOT_LEN]; /* 0x10 */ /* variable length */ 2645 } MPI3_SECURITY2_TRUSTED_ROOT, MPI3_POINTER PTR_MPI3_SECURITY2_TRUSTED_ROOT, 2646 Mpi3Security2TrustedRoot_t, MPI3_POINTER pMpi3Security2TrustedRoot_t; 2647 2648 /**** Defines for the TrustedRootFlags field ****/ 2649 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_MASK (0xF000) 2650 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_SHIFT (12) 2651 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DIGEST (0x0000) 2652 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DERCERT (0x1000) 2653 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) 2654 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) 2655 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) 2656 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002) 2657 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001) 2658 2659 typedef struct _MPI3_SECURITY_PAGE2 2660 { 2661 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2662 U32 Reserved08[2]; /* 0x08 */ 2663 MPI3_SECURITY_MAC Mac; /* 0x10 */ 2664 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ 2665 U32 Reserved90[3]; /* 0x90 */ 2666 U8 NumRoots; /* 0x9C */ 2667 U8 Reserved9D; /* 0x9D */ 2668 U16 RootElementSize; /* 0x9E */ 2669 MPI3_SECURITY2_TRUSTED_ROOT TrustedRoot[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; /* 0xA0 */ /* variable length */ 2670 } MPI3_SECURITY_PAGE2, MPI3_POINTER PTR_MPI3_SECURITY_PAGE2, 2671 Mpi3SecurityPage2_t, MPI3_POINTER pMpi3SecurityPage2_t; 2672 2673 /**** Defines for the PageVersion field ****/ 2674 #define MPI3_SECURITY2_PAGEVERSION (0x00) 2675 2676 2677 /***************************************************************************** 2678 * SAS IO Unit Configuration Pages * 2679 ****************************************************************************/ 2680 2681 /***************************************************************************** 2682 * SAS IO Unit Page 0 * 2683 ****************************************************************************/ 2684 typedef struct _MPI3_SAS_IO_UNIT0_PHY_DATA 2685 { 2686 U8 IOUnitPort; /* 0x00 */ 2687 U8 PortFlags; /* 0x01 */ 2688 U8 PhyFlags; /* 0x02 */ 2689 U8 NegotiatedLinkRate; /* 0x03 */ 2690 U16 ControllerPhyDeviceInfo; /* 0x04 */ 2691 U16 Reserved06; /* 0x06 */ 2692 U16 AttachedDevHandle; /* 0x08 */ 2693 U16 ControllerDevHandle; /* 0x0A */ 2694 U32 DiscoveryStatus; /* 0x0C */ 2695 U32 Reserved10; /* 0x10 */ 2696 } MPI3_SAS_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT0_PHY_DATA, 2697 Mpi3SasIOUnit0PhyData_t, MPI3_POINTER pMpi3SasIOUnit0PhyData_t; 2698 2699 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX 2700 #define MPI3_SAS_IO_UNIT0_PHY_MAX (1) 2701 #endif /* MPI3_SAS_IO_UNIT0_PHY_MAX */ 2702 2703 typedef struct _MPI3_SAS_IO_UNIT_PAGE0 2704 { 2705 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2706 U32 Reserved08; /* 0x08 */ 2707 U8 NumPhys; /* 0x0C */ 2708 U8 InitStatus; /* 0x0D */ 2709 U16 Reserved0E; /* 0x0E */ 2710 MPI3_SAS_IO_UNIT0_PHY_DATA PhyData[MPI3_SAS_IO_UNIT0_PHY_MAX]; /* 0x10 */ 2711 } MPI3_SAS_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE0, 2712 Mpi3SasIOUnitPage0_t, MPI3_POINTER pMpi3SasIOUnitPage0_t; 2713 2714 /**** Defines for the PageVersion field ****/ 2715 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 2716 2717 /**** Defines for the InitStatus field ****/ 2718 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 2719 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 2720 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 2721 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 2722 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 2723 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) 2724 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xF0) 2725 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xFF) 2726 2727 /**** Defines for the PortFlags field ****/ 2728 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 2729 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) 2730 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_SHIFT (0) 2731 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) 2732 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) 2733 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) 2734 2735 /**** Defines for the PhyFlags field ****/ 2736 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2737 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2738 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2739 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) 2740 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 2741 2742 /**** Use MPI3_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field ****/ 2743 2744 /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ 2745 2746 /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ 2747 2748 /***************************************************************************** 2749 * SAS IO Unit Page 1 * 2750 ****************************************************************************/ 2751 typedef struct _MPI3_SAS_IO_UNIT1_PHY_DATA 2752 { 2753 U8 IOUnitPort; /* 0x00 */ 2754 U8 PortFlags; /* 0x01 */ 2755 U8 PhyFlags; /* 0x02 */ 2756 U8 MaxMinLinkRate; /* 0x03 */ 2757 U16 ControllerPhyDeviceInfo; /* 0x04 */ 2758 U16 MaxTargetPortConnectTime; /* 0x06 */ 2759 U32 Reserved08; /* 0x08 */ 2760 } MPI3_SAS_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT1_PHY_DATA, 2761 Mpi3SasIOUnit1PhyData_t, MPI3_POINTER pMpi3SasIOUnit1PhyData_t; 2762 2763 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX 2764 #define MPI3_SAS_IO_UNIT1_PHY_MAX (1) 2765 #endif /* MPI3_SAS_IO_UNIT1_PHY_MAX */ 2766 2767 typedef struct _MPI3_SAS_IO_UNIT_PAGE1 2768 { 2769 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2770 U16 ControlFlags; /* 0x08 */ 2771 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2772 U16 AdditionalControlFlags; /* 0x0C */ 2773 U16 SASWideMaxQueueDepth; /* 0x0E */ 2774 U8 NumPhys; /* 0x10 */ 2775 U8 SATAMaxQDepth; /* 0x11 */ 2776 U16 Reserved12; /* 0x12 */ 2777 MPI3_SAS_IO_UNIT1_PHY_DATA PhyData[MPI3_SAS_IO_UNIT1_PHY_MAX]; /* 0x14 */ 2778 } MPI3_SAS_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE1, 2779 Mpi3SasIOUnitPage1_t, MPI3_POINTER pMpi3SasIOUnitPage1_t; 2780 2781 /**** Defines for the PageVersion field ****/ 2782 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 2783 2784 /**** Defines for the ControlFlags field ****/ 2785 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 2786 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2787 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2788 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2789 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2790 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2791 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2792 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2793 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2794 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 2795 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SHIFT (0) 2796 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 2797 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 2798 2799 /**** Defines for the AdditionalControlFlags field ****/ 2800 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2801 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2802 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2803 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2804 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2805 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2806 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2807 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2808 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2809 2810 /**** Defines for the PortFlags field ****/ 2811 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2812 2813 /**** Defines for the PhyFlags field ****/ 2814 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2815 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2816 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2817 2818 /**** Defines for the MaxMinLinkRate field ****/ 2819 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) 2820 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 2821 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xA0) 2822 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xB0) 2823 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xC0) 2824 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0F) 2825 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_SHIFT (0) 2826 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0A) 2827 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0B) 2828 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0C) 2829 2830 /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ 2831 2832 /***************************************************************************** 2833 * SAS IO Unit Page 2 * 2834 ****************************************************************************/ 2835 typedef struct _MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS 2836 { 2837 U8 ControlFlags; /* 0x00 */ 2838 U8 Reserved01; /* 0x01 */ 2839 U16 InactivityTimerExponent; /* 0x02 */ 2840 U8 SATAPartialTimeout; /* 0x04 */ 2841 U8 Reserved05; /* 0x05 */ 2842 U8 SATASlumberTimeout; /* 0x06 */ 2843 U8 Reserved07; /* 0x07 */ 2844 U8 SASPartialTimeout; /* 0x08 */ 2845 U8 Reserved09; /* 0x09 */ 2846 U8 SASSlumberTimeout; /* 0x0A */ 2847 U8 Reserved0B; /* 0x0B */ 2848 } MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, 2849 Mpi3SasIOUnit2PhyPmSettings_t, MPI3_POINTER pMpi3SasIOUnit2PhyPmSettings_t; 2850 2851 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 2852 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 2853 #endif /* MPI3_SAS_IO_UNIT2_PHY_MAX */ 2854 2855 typedef struct _MPI3_SAS_IO_UNIT_PAGE2 2856 { 2857 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2858 U8 NumPhys; /* 0x08 */ 2859 U8 Reserved09[3]; /* 0x09 */ 2860 U32 Reserved0C; /* 0x0C */ 2861 MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI3_SAS_IO_UNIT2_PHY_MAX]; /* 0x10 */ 2862 } MPI3_SAS_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE2, 2863 Mpi3SasIOUnitPage2_t, MPI3_POINTER pMpi3SasIOUnitPage2_t; 2864 2865 /**** Defines for the PageVersion field ****/ 2866 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 2867 2868 /**** Defines for the ControlFlags field ****/ 2869 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2870 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2871 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2872 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2873 2874 /**** Defines for the InactivityTimerExponent field ****/ 2875 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 2876 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 2877 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 2878 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 2879 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 2880 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 2881 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 2882 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 2883 2884 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 2885 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 2886 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 2887 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 2888 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 2889 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 2890 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 2891 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 2892 2893 /***************************************************************************** 2894 * SAS IO Unit Page 3 * 2895 ****************************************************************************/ 2896 typedef struct _MPI3_SAS_IO_UNIT_PAGE3 2897 { 2898 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2899 U32 Reserved08; /* 0x08 */ 2900 U32 PowerManagementCapabilities; /* 0x0C */ 2901 } MPI3_SAS_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE3, 2902 Mpi3SasIOUnitPage3_t, MPI3_POINTER pMpi3SasIOUnitPage3_t; 2903 2904 /**** Defines for the PageVersion field ****/ 2905 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 2906 2907 /**** Defines for the PowerManagementCapabilities field ****/ 2908 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2909 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2910 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2911 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2912 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2913 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2914 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2915 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2916 2917 2918 /***************************************************************************** 2919 * SAS Expander Configuration Pages * 2920 ****************************************************************************/ 2921 2922 /***************************************************************************** 2923 * SAS Expander Page 0 * 2924 ****************************************************************************/ 2925 typedef struct _MPI3_SAS_EXPANDER_PAGE0 2926 { 2927 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2928 U8 IOUnitPort; /* 0x08 */ 2929 U8 ReportGenLength; /* 0x09 */ 2930 U16 EnclosureHandle; /* 0x0A */ 2931 U32 Reserved0C; /* 0x0C */ 2932 U64 SASAddress; /* 0x10 */ 2933 U32 DiscoveryStatus; /* 0x18 */ 2934 U16 DevHandle; /* 0x1C */ 2935 U16 ParentDevHandle; /* 0x1E */ 2936 U16 ExpanderChangeCount; /* 0x20 */ 2937 U16 ExpanderRouteIndexes; /* 0x22 */ 2938 U8 NumPhys; /* 0x24 */ 2939 U8 SASLevel; /* 0x25 */ 2940 U16 Flags; /* 0x26 */ 2941 U16 STPBusInactivityTimeLimit; /* 0x28 */ 2942 U16 STPMaxConnectTimeLimit; /* 0x2A */ 2943 U16 STP_SMP_NexusLossTime; /* 0x2C */ 2944 U16 MaxNumRoutedSASAddresses; /* 0x2E */ 2945 U64 ActiveZoneManagerSASAddress; /* 0x30 */ 2946 U16 ZoneLockInactivityLimit; /* 0x38 */ 2947 U16 Reserved3A; /* 0x3A */ 2948 U8 TimeToReducedFunc; /* 0x3C */ 2949 U8 InitialTimeToReducedFunc; /* 0x3D */ 2950 U8 MaxReducedFuncTime; /* 0x3E */ 2951 U8 ExpStatus; /* 0x3F */ 2952 } MPI3_SAS_EXPANDER_PAGE0, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE0, 2953 Mpi3SasExpanderPage0_t, MPI3_POINTER pMpi3SasExpanderPage0_t; 2954 2955 /**** Defines for the PageVersion field ****/ 2956 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 2957 2958 /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ 2959 2960 /**** Defines for the Flags field ****/ 2961 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2962 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2963 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2964 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2965 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2966 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2967 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2968 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2969 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2970 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2971 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2972 2973 /**** Defines for the ExpStatus field ****/ 2974 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 2975 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 2976 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 2977 2978 /***************************************************************************** 2979 * SAS Expander Page 1 * 2980 ****************************************************************************/ 2981 typedef struct _MPI3_SAS_EXPANDER_PAGE1 2982 { 2983 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2984 U8 IOUnitPort; /* 0x08 */ 2985 U8 Reserved09[3]; /* 0x09 */ 2986 U8 NumPhys; /* 0x0C */ 2987 U8 Phy; /* 0x0D */ 2988 U16 NumTableEntriesProgrammed; /* 0x0E */ 2989 U8 ProgrammedLinkRate; /* 0x10 */ 2990 U8 HwLinkRate; /* 0x11 */ 2991 U16 AttachedDevHandle; /* 0x12 */ 2992 U32 PhyInfo; /* 0x14 */ 2993 U16 AttachedDeviceInfo; /* 0x18 */ 2994 U16 Reserved1A; /* 0x1A */ 2995 U16 ExpanderDevHandle; /* 0x1C */ 2996 U8 ChangeCount; /* 0x1E */ 2997 U8 NegotiatedLinkRate; /* 0x1F */ 2998 U8 PhyIdentifier; /* 0x20 */ 2999 U8 AttachedPhyIdentifier; /* 0x21 */ 3000 U8 Reserved22; /* 0x22 */ 3001 U8 DiscoveryInfo; /* 0x23 */ 3002 U32 AttachedPhyInfo; /* 0x24 */ 3003 U8 ZoneGroup; /* 0x28 */ 3004 U8 SelfConfigStatus; /* 0x29 */ 3005 U16 Reserved2A; /* 0x2A */ 3006 U16 Slot; /* 0x2C */ 3007 U16 SlotIndex; /* 0x2E */ 3008 } MPI3_SAS_EXPANDER_PAGE1, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE1, 3009 Mpi3SasExpanderPage1_t, MPI3_POINTER pMpi3SasExpanderPage1_t; 3010 3011 /**** Defines for the PageVersion field ****/ 3012 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 3013 3014 /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ 3015 3016 /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ 3017 3018 /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ 3019 3020 /**** Defines for the AttachedDeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ 3021 3022 /**** Defines for the NegotiatedLinkRate field - use use MPI3_SAS_NEG_LINK_RATE_ defines ****/ 3023 3024 /**** Defines for the DiscoveryInfo field ****/ 3025 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 3026 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 3027 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 3028 3029 /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ 3030 3031 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3032 3033 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 3034 3035 3036 /***************************************************************************** 3037 * SAS Expander Page 2 * 3038 ****************************************************************************/ 3039 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS 3040 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) 3041 #endif /* MPI3_SASEXPANDER2_MAX_NUM_PHYS */ 3042 3043 typedef struct _MPI3_SASEXPANDER2_PHY_ELEMENT 3044 { 3045 U8 LinkChangeCount; /* 0x00 */ 3046 U8 Reserved01; /* 0x01 */ 3047 U16 RateChangeCount; /* 0x02 */ 3048 U32 Reserved04; /* 0x04 */ 3049 } MPI3_SASEXPANDER2_PHY_ELEMENT, MPI3_POINTER PTR_MPI3_SASEXPANDER2_PHY_ELEMENT, 3050 Mpi3SasExpander2PhyElement_t, MPI3_POINTER pMpi3SasExpander2PhyElement_t; 3051 3052 typedef struct _MPI3_SAS_EXPANDER_PAGE2 3053 { 3054 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3055 U8 NumPhys; /* 0x08 */ 3056 U8 Reserved09; /* 0x09 */ 3057 U16 DevHandle; /* 0x0A */ 3058 U32 Reserved0C; /* 0x0C */ 3059 MPI3_SASEXPANDER2_PHY_ELEMENT Phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; /* 0x10 */ /* variable length */ 3060 3061 } MPI3_SAS_EXPANDER_PAGE2, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE2, 3062 Mpi3SasExpanderPage2_t, MPI3_POINTER pMpi3SasExpanderPage2_t; 3063 3064 /**** Defines for the PageVersion field ****/ 3065 #define MPI3_SASEXPANDER2_PAGEVERSION (0x00) 3066 3067 3068 /***************************************************************************** 3069 * SAS Port Configuration Pages * 3070 ****************************************************************************/ 3071 3072 /***************************************************************************** 3073 * SAS Port Page 0 * 3074 ****************************************************************************/ 3075 typedef struct _MPI3_SAS_PORT_PAGE0 3076 { 3077 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3078 U8 PortNumber; /* 0x08 */ 3079 U8 Reserved09; /* 0x09 */ 3080 U8 PortWidth; /* 0x0A */ 3081 U8 Reserved0B; /* 0x0B */ 3082 U8 ZoneGroup; /* 0x0C */ 3083 U8 Reserved0D[3]; /* 0x0D */ 3084 U64 SASAddress; /* 0x10 */ 3085 U16 DeviceInfo; /* 0x18 */ 3086 U16 Reserved1A; /* 0x1A */ 3087 U32 Reserved1C; /* 0x1C */ 3088 } MPI3_SAS_PORT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PORT_PAGE0, 3089 Mpi3SasPortPage0_t, MPI3_POINTER pMpi3SasPortPage0_t; 3090 3091 /**** Defines for the PageVersion field ****/ 3092 #define MPI3_SASPORT0_PAGEVERSION (0x00) 3093 3094 /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ 3095 3096 /***************************************************************************** 3097 * SAS PHY Configuration Pages * 3098 ****************************************************************************/ 3099 3100 /***************************************************************************** 3101 * SAS PHY Page 0 * 3102 ****************************************************************************/ 3103 typedef struct _MPI3_SAS_PHY_PAGE0 3104 { 3105 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3106 U16 OwnerDevHandle; /* 0x08 */ 3107 U16 Reserved0A; /* 0x0A */ 3108 U16 AttachedDevHandle; /* 0x0C */ 3109 U8 AttachedPhyIdentifier; /* 0x0E */ 3110 U8 Reserved0F; /* 0x0F */ 3111 U32 AttachedPhyInfo; /* 0x10 */ 3112 U8 ProgrammedLinkRate; /* 0x14 */ 3113 U8 HwLinkRate; /* 0x15 */ 3114 U8 ChangeCount; /* 0x16 */ 3115 U8 Flags; /* 0x17 */ 3116 U32 PhyInfo; /* 0x18 */ 3117 U8 NegotiatedLinkRate; /* 0x1C */ 3118 U8 Reserved1D[3]; /* 0x1D */ 3119 U16 Slot; /* 0x20 */ 3120 U16 SlotIndex; /* 0x22 */ 3121 } MPI3_SAS_PHY_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE0, 3122 Mpi3SasPhyPage0_t, MPI3_POINTER pMpi3SasPhyPage0_t; 3123 3124 /**** Defines for the PageVersion field ****/ 3125 #define MPI3_SASPHY0_PAGEVERSION (0x00) 3126 3127 /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ 3128 3129 /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ 3130 3131 /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ 3132 3133 /**** Defines for the Flags field ****/ 3134 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 3135 3136 /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ 3137 3138 /**** Defines for the NegotiatedLinkRate field - use MPI3_SAS_NEG_LINK_RATE_ defines ****/ 3139 3140 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3141 3142 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 3143 3144 /***************************************************************************** 3145 * SAS PHY Page 1 * 3146 ****************************************************************************/ 3147 typedef struct _MPI3_SAS_PHY_PAGE1 3148 { 3149 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3150 U32 Reserved08; /* 0x08 */ 3151 U32 InvalidDwordCount; /* 0x0C */ 3152 U32 RunningDisparityErrorCount; /* 0x10 */ 3153 U32 LossDwordSynchCount; /* 0x14 */ 3154 U32 PhyResetProblemCount; /* 0x18 */ 3155 } MPI3_SAS_PHY_PAGE1, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE1, 3156 Mpi3SasPhyPage1_t, MPI3_POINTER pMpi3SasPhyPage1_t; 3157 3158 /**** Defines for the PageVersion field ****/ 3159 #define MPI3_SASPHY1_PAGEVERSION (0x00) 3160 3161 /***************************************************************************** 3162 * SAS PHY Page 2 * 3163 ****************************************************************************/ 3164 typedef struct _MPI3_SAS_PHY2_PHY_EVENT 3165 { 3166 U8 PhyEventCode; /* 0x00 */ 3167 U8 Reserved01[3]; /* 0x01 */ 3168 U32 PhyEventInfo; /* 0x04 */ 3169 } MPI3_SAS_PHY2_PHY_EVENT, MPI3_POINTER PTR_MPI3_SAS_PHY2_PHY_EVENT, 3170 Mpi3SasPhy2PhyEvent_t, MPI3_POINTER pMpi3SasPhy2PhyEvent_t; 3171 3172 /**** Defines for the PhyEventCode field - use MPI3_SASPHY3_EVENT_CODE_ defines */ 3173 3174 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 3175 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 3176 #endif /* MPI3_SAS_PHY2_PHY_EVENT_MAX */ 3177 3178 typedef struct _MPI3_SAS_PHY_PAGE2 3179 { 3180 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3181 U32 Reserved08; /* 0x08 */ 3182 U8 NumPhyEvents; /* 0x0C */ 3183 U8 Reserved0D[3]; /* 0x0D */ 3184 MPI3_SAS_PHY2_PHY_EVENT PhyEvent[MPI3_SAS_PHY2_PHY_EVENT_MAX]; /* 0x10 */ 3185 } MPI3_SAS_PHY_PAGE2, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE2, 3186 Mpi3SasPhyPage2_t, MPI3_POINTER pMpi3SasPhyPage2_t; 3187 3188 /**** Defines for the PageVersion field ****/ 3189 #define MPI3_SASPHY2_PAGEVERSION (0x00) 3190 3191 /***************************************************************************** 3192 * SAS PHY Page 3 * 3193 ****************************************************************************/ 3194 typedef struct _MPI3_SAS_PHY3_PHY_EVENT_CONFIG 3195 { 3196 U8 PhyEventCode; /* 0x00 */ 3197 U8 Reserved01[3]; /* 0x01 */ 3198 U8 CounterType; /* 0x04 */ 3199 U8 ThresholdWindow; /* 0x05 */ 3200 U8 TimeUnits; /* 0x06 */ 3201 U8 Reserved07; /* 0x07 */ 3202 U32 EventThreshold; /* 0x08 */ 3203 U16 ThresholdFlags; /* 0x0C */ 3204 U16 Reserved0E; /* 0x0E */ 3205 } MPI3_SAS_PHY3_PHY_EVENT_CONFIG, MPI3_POINTER PTR_MPI3_SAS_PHY3_PHY_EVENT_CONFIG, 3206 Mpi3SasPhy3PhyEventConfig_t, MPI3_POINTER pMpi3SasPhy3PhyEventConfig_t; 3207 3208 /**** Defines for the PhyEventCode field ****/ 3209 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3210 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3211 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3212 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3213 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3214 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3215 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3216 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 3217 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 3218 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3219 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3220 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3221 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3222 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3223 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3224 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3225 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3226 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3227 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3228 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3229 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3230 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3231 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3232 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3233 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2F) 3234 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3235 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3236 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3237 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3238 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3239 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3240 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3241 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3242 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3243 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3244 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3245 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3246 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3247 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3248 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3249 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3250 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3251 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3252 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3253 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3254 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3255 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3256 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3257 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3258 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3259 3260 /**** Defines for the CounterType field ****/ 3261 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3262 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3263 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3264 3265 /**** Defines for the TimeUnits field ****/ 3266 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3267 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3268 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3269 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3270 3271 /**** Defines for the ThresholdFlags field ****/ 3272 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3273 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3274 3275 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 3276 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 3277 #endif /* MPI3_SAS_PHY3_PHY_EVENT_MAX */ 3278 3279 typedef struct _MPI3_SAS_PHY_PAGE3 3280 { 3281 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3282 U32 Reserved08; /* 0x08 */ 3283 U8 NumPhyEvents; /* 0x0C */ 3284 U8 Reserved0D[3]; /* 0x0D */ 3285 MPI3_SAS_PHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI3_SAS_PHY3_PHY_EVENT_MAX]; /* 0x10 */ 3286 } MPI3_SAS_PHY_PAGE3, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE3, 3287 Mpi3SasPhyPage3_t, MPI3_POINTER pMpi3SasPhyPage3_t; 3288 3289 /**** Defines for the PageVersion field ****/ 3290 #define MPI3_SASPHY3_PAGEVERSION (0x00) 3291 3292 /***************************************************************************** 3293 * SAS PHY Page 4 * 3294 ****************************************************************************/ 3295 typedef struct _MPI3_SAS_PHY_PAGE4 3296 { 3297 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3298 U8 Reserved08[3]; /* 0x08 */ 3299 U8 Flags; /* 0x0B */ 3300 U8 InitialFrame[28]; /* 0x0C */ 3301 } MPI3_SAS_PHY_PAGE4, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE4, 3302 Mpi3SasPhyPage4_t, MPI3_POINTER pMpi3SasPhyPage4_t; 3303 3304 /**** Defines for the PageVersion field ****/ 3305 #define MPI3_SASPHY4_PAGEVERSION (0x00) 3306 3307 /**** Defines for the Flags field ****/ 3308 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 3309 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 3310 3311 3312 /***************************************************************************** 3313 * Common definitions used by PCIe Configuration Pages * 3314 ****************************************************************************/ 3315 3316 /**** Defines for NegotiatedLinkRates ****/ 3317 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 3318 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 3319 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0F) 3320 #define MPI3_PCIE_NEG_LINK_RATE_SHIFT (0) 3321 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3322 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3323 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 3324 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 3325 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 3326 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 3327 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 3328 3329 /**** Defines for Enabled ASPM States ****/ 3330 #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) 3331 #define MPI3_PCIE_ASPM_ENABLE_L0s (0x1) 3332 #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) 3333 #define MPI3_PCIE_ASPM_ENABLE_L0s_L1 (0x3) 3334 3335 /**** Defines for Enabled ASPM States ****/ 3336 #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) 3337 #define MPI3_PCIE_ASPM_SUPPORT_L0s (0x1) 3338 #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) 3339 #define MPI3_PCIE_ASPM_SUPPORT_L0s_L1 (0x3) 3340 3341 /***************************************************************************** 3342 * PCIe IO Unit Configuration Pages * 3343 ****************************************************************************/ 3344 3345 /***************************************************************************** 3346 * PCIe IO Unit Page 0 * 3347 ****************************************************************************/ 3348 typedef struct _MPI3_PCIE_IO_UNIT0_PHY_DATA 3349 { 3350 U8 Link; /* 0x00 */ 3351 U8 LinkFlags; /* 0x01 */ 3352 U8 PhyFlags; /* 0x02 */ 3353 U8 NegotiatedLinkRate; /* 0x03 */ 3354 U16 AttachedDevHandle; /* 0x04 */ 3355 U16 ControllerDevHandle; /* 0x06 */ 3356 U32 EnumerationStatus; /* 0x08 */ 3357 U8 IOUnitPort; /* 0x0C */ 3358 U8 Reserved0D[3]; /* 0x0D */ 3359 } MPI3_PCIE_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT0_PHY_DATA, 3360 Mpi3PcieIOUnit0PhyData_t, MPI3_POINTER pMpi3PcieIOUnit0PhyData_t; 3361 3362 /**** Defines for the LinkFlags field ****/ 3363 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 3364 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_SHIFT (4) 3365 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 3366 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 3367 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 3368 3369 /**** Defines for the PhyFlags field ****/ 3370 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3371 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 3372 3373 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3374 3375 /**** Defines for the EnumerationStatus field ****/ 3376 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 3377 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3378 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 3379 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 3380 3381 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 3382 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 3383 #endif /* MPI3_PCIE_IO_UNIT0_PHY_MAX */ 3384 3385 typedef struct _MPI3_PCIE_IO_UNIT_PAGE0 3386 { 3387 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3388 U32 Reserved08; /* 0x08 */ 3389 U8 NumPhys; /* 0x0C */ 3390 U8 InitStatus; /* 0x0D */ 3391 U8 ASPM; /* 0x0E */ 3392 U8 Reserved0F; /* 0x0F */ 3393 MPI3_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT0_PHY_MAX]; /* 0x10 */ 3394 } MPI3_PCIE_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE0, 3395 Mpi3PcieIOUnitPage0_t, MPI3_POINTER pMpi3PcieIOUnitPage0_t; 3396 3397 /**** Defines for the PageVersion field ****/ 3398 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 3399 3400 /**** Defines for the InitStatus field ****/ 3401 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 3402 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 3403 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 3404 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 3405 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 3406 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 3407 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 3408 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 3409 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 3410 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xF0) 3411 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xFF) 3412 3413 /**** Defines for the ASPM field ****/ 3414 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xC0) 3415 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) 3416 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) 3417 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) 3418 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for field values ***/ 3419 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0C) 3420 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) 3421 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) 3422 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) 3423 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for field values ***/ 3424 3425 /***************************************************************************** 3426 * PCIe IO Unit Page 1 * 3427 ****************************************************************************/ 3428 typedef struct _MPI3_PCIE_IO_UNIT1_PHY_DATA 3429 { 3430 U8 Link; /* 0x00 */ 3431 U8 LinkFlags; /* 0x01 */ 3432 U8 PhyFlags; /* 0x02 */ 3433 U8 MaxMinLinkRate; /* 0x03 */ 3434 U32 Reserved04; /* 0x04 */ 3435 U32 Reserved08; /* 0x08 */ 3436 } MPI3_PCIE_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT1_PHY_DATA, 3437 Mpi3PcieIOUnit1PhyData_t, MPI3_POINTER pMpi3PcieIOUnit1PhyData_t; 3438 3439 /**** Defines for the LinkFlags field ****/ 3440 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 3441 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_SHIFT (0) 3442 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 3443 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 3444 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 3445 3446 /**** Defines for the PhyFlags field ****/ 3447 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3448 3449 /**** Defines for the MaxMinLinkRate ****/ 3450 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) 3451 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 3452 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 3453 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 3454 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 3455 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 3456 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 3457 3458 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 3459 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 3460 #endif /* MPI3_PCIE_IO_UNIT1_PHY_MAX */ 3461 3462 typedef struct _MPI3_PCIE_IO_UNIT_PAGE1 3463 { 3464 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3465 U32 ControlFlags; /* 0x08 */ 3466 U32 Reserved0C; /* 0x0C */ 3467 U8 NumPhys; /* 0x10 */ 3468 U8 Reserved11; /* 0x11 */ 3469 U8 ASPM; /* 0x12 */ 3470 U8 Reserved13; /* 0x13 */ 3471 MPI3_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT1_PHY_MAX]; /* 0x14 */ 3472 } MPI3_PCIE_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE1, 3473 Mpi3PcieIOUnitPage1_t, MPI3_POINTER pMpi3PcieIOUnitPage1_t; 3474 3475 /**** Defines for the PageVersion field ****/ 3476 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 3477 3478 /**** Defines for the ControlFlags field ****/ 3479 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xE0000000) 3480 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_SHIFT (29) 3481 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) 3482 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) 3483 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) 3484 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) 3485 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1C000000) 3486 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_SHIFT (26) 3487 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) 3488 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ENABLE (0x04000000) 3489 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DISABLE (0x08000000) 3490 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0C000000) 3491 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PARTIAL_CAPACITY_ENABLE (0x00000100) 3492 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) 3493 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040) 3494 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030) 3495 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) 3496 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000) 3497 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) 3498 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) 3499 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000F) 3500 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_SHIFT (0) 3501 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) 3502 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) 3503 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) 3504 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004) 3505 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005) 3506 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006) 3507 3508 /**** Defines for the ASPM field ****/ 3509 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0C) 3510 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) 3511 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) 3512 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) 3513 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ 3514 3515 /***************************************************************************** 3516 * PCIe IO Unit Page 2 * 3517 ****************************************************************************/ 3518 typedef struct _MPI3_PCIE_IO_UNIT_PAGE2 3519 { 3520 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3521 U16 NVMeMaxQDx1; /* 0x08 */ 3522 U16 NVMeMaxQDx2; /* 0x0A */ 3523 U8 NVMeAbortTO; /* 0x0C */ 3524 U8 Reserved0D; /* 0x0D */ 3525 U16 NVMeMaxQDx4; /* 0x0E */ 3526 } MPI3_PCIE_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE2, 3527 Mpi3PcieIOUnitPage2_t, MPI3_POINTER pMpi3PcieIOUnitPage2_t; 3528 3529 /**** Defines for the PageVersion field ****/ 3530 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 3531 3532 /***************************************************************************** 3533 * PCIe IO Unit Page 3 * 3534 ****************************************************************************/ 3535 3536 /**** Defines for Error Indexes ****/ 3537 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) 3538 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) 3539 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) 3540 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) 3541 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) 3542 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) 3543 3544 3545 typedef struct _MPI3_PCIE_IO_UNIT3_ERROR 3546 { 3547 U16 ThresholdCount; /* 0x00 */ 3548 U16 Reserved02; /* 0x02 */ 3549 } MPI3_PCIE_IO_UNIT3_ERROR, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT3_ERROR, 3550 Mpi3PcieIOUnit3Error_t, MPI3_POINTER pMpi3PcieIOUnit3Error_t; 3551 3552 typedef struct _MPI3_PCIE_IO_UNIT_PAGE3 3553 { 3554 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3555 U8 ThresholdWindow; /* 0x08 */ 3556 U8 ThresholdAction; /* 0x09 */ 3557 U8 EscalationCount; /* 0x0A */ 3558 U8 EscalationAction; /* 0x0B */ 3559 U8 NumErrors; /* 0x0C */ 3560 U8 Reserved0D[3]; /* 0x0D */ 3561 MPI3_PCIE_IO_UNIT3_ERROR Error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; /* 0x10 */ 3562 } MPI3_PCIE_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE3, 3563 Mpi3PcieIOUnitPage3_t, MPI3_POINTER pMpi3PcieIOUnitPage3_t; 3564 3565 /**** Defines for the PageVersion field ****/ 3566 #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) 3567 3568 /**** Defines for the ThresholdAction and EscalationAction fields ****/ 3569 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) 3570 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) 3571 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) 3572 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) 3573 3574 /**** Defines for Error Indexes - use MPI3_PCIEIOUNIT3_ERROR_ defines ****/ 3575 3576 /***************************************************************************** 3577 * PCIe Switch Configuration Pages * 3578 ****************************************************************************/ 3579 3580 /***************************************************************************** 3581 * PCIe Switch Page 0 * 3582 ****************************************************************************/ 3583 typedef struct _MPI3_PCIE_SWITCH_PAGE0 3584 { 3585 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3586 U8 IOUnitPort; /* 0x08 */ 3587 U8 SwitchStatus; /* 0x09 */ 3588 U8 Reserved0A[2]; /* 0x0A */ 3589 U16 DevHandle; /* 0x0C */ 3590 U16 ParentDevHandle; /* 0x0E */ 3591 U8 NumPorts; /* 0x10 */ 3592 U8 PCIeLevel; /* 0x11 */ 3593 U16 Reserved12; /* 0x12 */ 3594 U32 Reserved14; /* 0x14 */ 3595 U32 Reserved18; /* 0x18 */ 3596 U32 Reserved1C; /* 0x1C */ 3597 } MPI3_PCIE_SWITCH_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE0, 3598 Mpi3PcieSwitchPage0_t, MPI3_POINTER pMpi3PcieSwitchPage0_t; 3599 3600 /**** Defines for the PageVersion field ****/ 3601 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 3602 3603 /**** Defines for the SwitchStatus field ****/ 3604 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 3605 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 3606 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 3607 3608 /***************************************************************************** 3609 * PCIe Switch Page 1 * 3610 ****************************************************************************/ 3611 typedef struct _MPI3_PCIE_SWITCH_PAGE1 3612 { 3613 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3614 U8 IOUnitPort; /* 0x08 */ 3615 U8 Flags; /* 0x09 */ 3616 U16 Reserved0A; /* 0x0A */ 3617 U8 NumPorts; /* 0x0C */ 3618 U8 PortNum; /* 0x0D */ 3619 U16 AttachedDevHandle; /* 0x0E */ 3620 U16 SwitchDevHandle; /* 0x10 */ 3621 U8 NegotiatedPortWidth; /* 0x12 */ 3622 U8 NegotiatedLinkRate; /* 0x13 */ 3623 U16 Slot; /* 0x14 */ 3624 U16 SlotIndex; /* 0x16 */ 3625 U32 Reserved18; /* 0x18 */ 3626 } MPI3_PCIE_SWITCH_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE1, 3627 Mpi3PcieSwitchPage1_t, MPI3_POINTER pMpi3PcieSwitchPage1_t; 3628 3629 /**** Defines for the PageVersion field ****/ 3630 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 3631 3632 /**** Defines for the Flags field ****/ 3633 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0C) 3634 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) 3635 3636 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPMState field values ***/ 3637 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) 3638 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) 3639 3640 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPMSupport field values ***/ 3641 3642 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3643 3644 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3645 3646 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 3647 3648 /***************************************************************************** 3649 * PCIe Switch Page 2 * 3650 ****************************************************************************/ 3651 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS 3652 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) 3653 #endif /* MPI3_PCIESWITCH2_MAX_NUM_PORTS */ 3654 3655 typedef struct _MPI3_PCIESWITCH2_PORT_ELEMENT 3656 { 3657 U16 LinkChangeCount; /* 0x00 */ 3658 U16 RateChangeCount; /* 0x02 */ 3659 U32 Reserved04; /* 0x04 */ 3660 } MPI3_PCIESWITCH2_PORT_ELEMENT, MPI3_POINTER PTR_MPI3_PCIESWITCH2_PORT_ELEMENT, 3661 Mpi3PcieSwitch2PortElement_t, MPI3_POINTER pMpi3PcieSwitch2PortElement_t; 3662 3663 typedef struct _MPI3_PCIE_SWITCH_PAGE2 3664 { 3665 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3666 U8 NumPorts; /* 0x08 */ 3667 U8 Reserved09; /* 0x09 */ 3668 U16 DevHandle; /* 0x0A */ 3669 U32 Reserved0C; /* 0x0C */ 3670 MPI3_PCIESWITCH2_PORT_ELEMENT Port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; /* 0x10 */ /* variable length */ 3671 } MPI3_PCIE_SWITCH_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE2, 3672 Mpi3PcieSwitchPage2_t, MPI3_POINTER pMpi3PcieSwitchPage2_t; 3673 3674 /**** Defines for the PageVersion field ****/ 3675 #define MPI3_PCIESWITCH2_PAGEVERSION (0x00) 3676 3677 /***************************************************************************** 3678 * PCIe Link Configuration Pages * 3679 ****************************************************************************/ 3680 3681 /***************************************************************************** 3682 * PCIe Link Page 0 * 3683 ****************************************************************************/ 3684 typedef struct _MPI3_PCIE_LINK_PAGE0 3685 { 3686 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3687 U8 Link; /* 0x08 */ 3688 U8 Reserved09[3]; /* 0x09 */ 3689 U32 Reserved0C; /* 0x0C */ 3690 U32 ReceiverErrorCount; /* 0x10 */ 3691 U32 RecoveryCount; /* 0x14 */ 3692 U32 CorrErrorMsgCount; /* 0x18 */ 3693 U32 NonFatalErrorMsgCount; /* 0x1C */ 3694 U32 FatalErrorMsgCount; /* 0x20 */ 3695 U32 NonFatalErrorCount; /* 0x24 */ 3696 U32 FatalErrorCount; /* 0x28 */ 3697 U32 BadDLLPCount; /* 0x2C */ 3698 U32 BadTLPCount; /* 0x30 */ 3699 } MPI3_PCIE_LINK_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_LINK_PAGE0, 3700 Mpi3PcieLinkPage0_t, MPI3_POINTER pMpi3PcieLinkPage0_t; 3701 3702 /**** Defines for the PageVersion field ****/ 3703 #define MPI3_PCIELINK0_PAGEVERSION (0x00) 3704 3705 3706 /***************************************************************************** 3707 * Enclosure Configuration Pages * 3708 ****************************************************************************/ 3709 3710 /***************************************************************************** 3711 * Enclosure Page 0 * 3712 ****************************************************************************/ 3713 typedef struct _MPI3_ENCLOSURE_PAGE0 3714 { 3715 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3716 U64 EnclosureLogicalID; /* 0x08 */ 3717 U16 Flags; /* 0x10 */ 3718 U16 EnclosureHandle; /* 0x12 */ 3719 U16 NumSlots; /* 0x14 */ 3720 U16 Reserved16; /* 0x16 */ 3721 U8 IOUnitPort; /* 0x18 */ 3722 U8 EnclosureLevel; /* 0x19 */ 3723 U16 SEPDevHandle; /* 0x1A */ 3724 U8 ChassisSlot; /* 0x1C */ 3725 U8 Reserved1D[3]; /* 0x1D */ 3726 U32 ReceptacleIDs; /* 0x20 */ 3727 U32 Reserved24; /* 0x24 */ 3728 } MPI3_ENCLOSURE_PAGE0, MPI3_POINTER PTR_MPI3_ENCLOSURE_PAGE0, 3729 Mpi3EnclosurePage0_t, MPI3_POINTER pMpi3EnclosurePage0_t; 3730 3731 /**** Defines for the PageVersion field ****/ 3732 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 3733 3734 /**** Defines for the Flags field ****/ 3735 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xC000) 3736 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SHIFT (0xC000) 3737 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 3738 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 3739 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 3740 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3741 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 3742 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_SHIFT (4) 3743 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 3744 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 3745 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000F) 3746 #define MPI3_ENCLS0_FLAGS_MNG_SHIFT (0) 3747 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3748 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3749 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 3750 3751 /**** Defines for the ReceptacleIDs field ****/ 3752 #define MPI3_ENCLS0_RECEPTACLEIDS_NOT_REPORTED (0x00000000) 3753 3754 /***************************************************************************** 3755 * Device Configuration Pages * 3756 ****************************************************************************/ 3757 3758 /***************************************************************************** 3759 * Common definitions used by Device Configuration Pages * 3760 ****************************************************************************/ 3761 3762 /**** Defines for the DeviceForm field ****/ 3763 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 3764 #define MPI3_DEVICE_DEVFORM_PCIE (0x01) 3765 #define MPI3_DEVICE_DEVFORM_VD (0x02) 3766 3767 /***************************************************************************** 3768 * Device Page 0 * 3769 ****************************************************************************/ 3770 typedef struct _MPI3_DEVICE0_SAS_SATA_FORMAT 3771 { 3772 U64 SASAddress; /* 0x00 */ 3773 U16 Flags; /* 0x08 */ 3774 U16 DeviceInfo; /* 0x0A */ 3775 U8 PhyNum; /* 0x0C */ 3776 U8 AttachedPhyIdentifier; /* 0x0D */ 3777 U8 MaxPortConnections; /* 0x0E */ 3778 U8 ZoneGroup; /* 0x0F */ 3779 } MPI3_DEVICE0_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_SAS_SATA_FORMAT, 3780 Mpi3Device0SasSataFormat_t, MPI3_POINTER pMpi3Device0SasSataFormat_t; 3781 3782 /**** Defines for the Flags field ****/ 3783 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) 3784 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 3785 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 3786 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 3787 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 3788 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 3789 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 3790 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 3791 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 3792 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 3793 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 3794 3795 /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) ****/ 3796 3797 typedef struct _MPI3_DEVICE0_PCIE_FORMAT 3798 { 3799 U8 SupportedLinkRates; /* 0x00 */ 3800 U8 MaxPortWidth; /* 0x01 */ 3801 U8 NegotiatedPortWidth; /* 0x02 */ 3802 U8 NegotiatedLinkRate; /* 0x03 */ 3803 U8 PortNum; /* 0x04 */ 3804 U8 ControllerResetTO; /* 0x05 */ 3805 U16 DeviceInfo; /* 0x06 */ 3806 U32 MaximumDataTransferSize; /* 0x08 */ 3807 U32 Capabilities; /* 0x0C */ 3808 U16 NOIOB; /* 0x10 */ 3809 U8 NVMeAbortTO; /* 0x12 */ 3810 U8 PageSize; /* 0x13 */ 3811 U16 ShutdownLatency; /* 0x14 */ 3812 U8 RecoveryInfo; /* 0x16 */ 3813 U8 Reserved17; /* 0x17 */ 3814 } MPI3_DEVICE0_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_PCIE_FORMAT, 3815 Mpi3Device0PcieFormat_t, MPI3_POINTER pMpi3Device0PcieFormat_t; 3816 3817 /**** Defines for the SupportedLinkRates field ****/ 3818 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 3819 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 3820 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 3821 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 3822 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 3823 3824 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3825 3826 /**** Defines for DeviceInfo bitfield ****/ 3827 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) 3828 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SHIFT (0) 3829 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 3830 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 3831 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 3832 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 3833 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) 3834 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) 3835 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ 3836 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00C0) 3837 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) 3838 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) 3839 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) 3840 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) 3841 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00C0) 3842 3843 3844 /**** Defines for the Capabilities field ****/ 3845 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) 3846 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 3847 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 3848 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) 3849 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) 3850 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 3851 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 3852 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000C0) 3853 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) 3854 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPM field values ***/ 3855 3856 /**** Defines for the RecoveryInfo field ****/ 3857 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xE0) 3858 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_SHIFT (5) 3859 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) 3860 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) 3861 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1F) 3862 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_SHIFT (0) 3863 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) 3864 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) 3865 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) 3866 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) 3867 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) 3868 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) 3869 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PARTIAL_CAP (0x06) 3870 3871 typedef struct _MPI3_DEVICE0_VD_FORMAT 3872 { 3873 U8 VdState; /* 0x00 */ 3874 U8 RAIDLevel; /* 0x01 */ 3875 U16 DeviceInfo; /* 0x02 */ 3876 U16 Flags; /* 0x04 */ 3877 U16 IOThrottleGroup; /* 0x06 */ 3878 U16 IOThrottleGroupLow; /* 0x08 */ 3879 U16 IOThrottleGroupHigh; /* 0x0A */ 3880 U32 Reserved0C; /* 0x0C */ 3881 } MPI3_DEVICE0_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_VD_FORMAT, 3882 Mpi3Device0VdFormat_t, MPI3_POINTER pMpi3Device0VdFormat_t; 3883 3884 /**** Defines for the VdState field ****/ 3885 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 3886 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 3887 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 3888 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 3889 3890 /**** Defines for RAIDLevel field ****/ 3891 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 3892 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 3893 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 3894 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 3895 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 3896 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 3897 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 3898 3899 /**** Defines for DeviceInfo field ****/ 3900 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 3901 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 3902 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 3903 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 3904 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 3905 3906 /**** Defines for the Flags field ****/ 3907 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xF000) 3908 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) 3909 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003) 3910 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SHIFT (0) 3911 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000) 3912 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001) 3913 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002) 3914 3915 typedef union _MPI3_DEVICE0_DEV_SPEC_FORMAT 3916 { 3917 MPI3_DEVICE0_SAS_SATA_FORMAT SasSataFormat; 3918 MPI3_DEVICE0_PCIE_FORMAT PcieFormat; 3919 MPI3_DEVICE0_VD_FORMAT VdFormat; 3920 } MPI3_DEVICE0_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_DEV_SPEC_FORMAT, 3921 Mpi3Device0DevSpecFormat_t, MPI3_POINTER pMpi3Device0DevSpecFormat_t; 3922 3923 typedef struct _MPI3_DEVICE_PAGE0 3924 { 3925 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3926 U16 DevHandle; /* 0x08 */ 3927 U16 ParentDevHandle; /* 0x0A */ 3928 U16 Slot; /* 0x0C */ 3929 U16 EnclosureHandle; /* 0x0E */ 3930 U64 WWID; /* 0x10 */ 3931 U16 PersistentID; /* 0x18 */ 3932 U8 IOUnitPort; /* 0x1A */ 3933 U8 AccessStatus; /* 0x1B */ 3934 U16 Flags; /* 0x1C */ 3935 U16 Reserved1E; /* 0x1E */ 3936 U16 SlotIndex; /* 0x20 */ 3937 U16 QueueDepth; /* 0x22 */ 3938 U8 Reserved24[3]; /* 0x24 */ 3939 U8 DeviceForm; /* 0x27 */ 3940 MPI3_DEVICE0_DEV_SPEC_FORMAT DeviceSpecific; /* 0x28 */ 3941 } MPI3_DEVICE_PAGE0, MPI3_POINTER PTR_MPI3_DEVICE_PAGE0, 3942 Mpi3DevicePage0_t, MPI3_POINTER pMpi3DevicePage0_t; 3943 3944 /**** Defines for the PageVersion field ****/ 3945 #define MPI3_DEVICE0_PAGEVERSION (0x00) 3946 3947 /**** Defines for the ParentDevHandle field ****/ 3948 #define MPI3_DEVICE0_PARENT_INVALID (0xFFFF) 3949 3950 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3951 3952 /**** Defines for the EnclosureHandle field ****/ 3953 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) 3954 3955 /**** Defines for the WWID field ****/ 3956 #define MPI3_DEVICE0_WWID_INVALID (0xFFFFFFFFFFFFFFFF) 3957 3958 /**** Defines for the PersistentID field ****/ 3959 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xFFFF) 3960 3961 /**** Defines for the IOUnitPort field ****/ 3962 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xFF) 3963 3964 /**** Defines for the AccessStatus field ****/ 3965 /* Generic Access Status Codes */ 3966 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 3967 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 3968 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 3969 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 3970 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 3971 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 3972 #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) 3973 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) 3974 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0F) 3975 /* SAS Access Status Codes */ 3976 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 3977 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 3978 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 3979 #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1F) 3980 /* SATA Access Status Codes */ 3981 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 3982 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 3983 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 3984 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 3985 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 3986 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 3987 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 3988 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 3989 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 3990 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 3991 #define MPI3_DEVICE0_ASTATUS_SIF_DEVICE_FAULT (0x2A) 3992 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2F) 3993 /* PCIe Access Status Codes */ 3994 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 3995 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 3996 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 3997 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 3998 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) 3999 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3F) 4000 /* NVMe Access Status Codes */ 4001 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 4002 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 4003 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 4004 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 4005 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 4006 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 4007 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 4008 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 4009 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 4010 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 4011 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4A) 4012 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4B) 4013 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4C) 4014 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4D) 4015 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4E) 4016 #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4F) 4017 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) 4018 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) 4019 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) 4020 #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5F) 4021 /* Virtual Device Access Status Codes */ 4022 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) 4023 #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8F) 4024 4025 /**** Defines for the Flags field ****/ 4026 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xE000) 4027 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_SHIFT (13) 4028 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) 4029 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) 4030 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) 4031 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 4032 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) 4033 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 4034 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 4035 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 4036 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 4037 4038 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ defines ****/ 4039 4040 /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ 4041 4042 /**** Defines for the QueueDepth field ****/ 4043 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 4044 4045 4046 /***************************************************************************** 4047 * Device Page 1 * 4048 ****************************************************************************/ 4049 typedef struct _MPI3_DEVICE1_SAS_SATA_FORMAT 4050 { 4051 U32 Reserved00; /* 0x00 */ 4052 } MPI3_DEVICE1_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_SAS_SATA_FORMAT, 4053 Mpi3Device1SasSataFormat_t, MPI3_POINTER pMpi3Device1SasSataFormat_t; 4054 4055 typedef struct _MPI3_DEVICE1_PCIE_FORMAT 4056 { 4057 U16 VendorID; /* 0x00 */ 4058 U16 DeviceID; /* 0x02 */ 4059 U16 SubsystemVendorID; /* 0x04 */ 4060 U16 SubsystemID; /* 0x06 */ 4061 U16 ReadyTimeout; /* 0x08 */ 4062 U16 Reserved0A; /* 0x0A */ 4063 U8 RevisionID; /* 0x0C */ 4064 U8 Reserved0D; /* 0x0D */ 4065 U16 PCIParameters; /* 0x0E */ 4066 } MPI3_DEVICE1_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_PCIE_FORMAT, 4067 Mpi3Device1PcieFormat_t, MPI3_POINTER pMpi3Device1PcieFormat_t; 4068 4069 /**** Defines for the PCIParameters field ****/ 4070 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 4071 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 4072 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 4073 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 4074 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 4075 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 4076 4077 /*** MaxReadRequestSize, CurrentMaxPayloadSize, and MaxPayloadSizeSupported ***/ 4078 /*** all use the size definitions above - shifted to the proper position ***/ 4079 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01C0) 4080 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 4081 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 4082 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 4083 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 4084 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 4085 4086 typedef struct _MPI3_DEVICE1_VD_FORMAT 4087 { 4088 U32 Reserved00; /* 0x00 */ 4089 } MPI3_DEVICE1_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_VD_FORMAT, 4090 Mpi3Device1VdFormat_t, MPI3_POINTER pMpi3Device1VdFormat_t; 4091 4092 typedef union _MPI3_DEVICE1_DEV_SPEC_FORMAT 4093 { 4094 MPI3_DEVICE1_SAS_SATA_FORMAT SasSataFormat; 4095 MPI3_DEVICE1_PCIE_FORMAT PcieFormat; 4096 MPI3_DEVICE1_VD_FORMAT VdFormat; 4097 } MPI3_DEVICE1_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_DEV_SPEC_FORMAT, 4098 Mpi3Device1DevSpecFormat_t, MPI3_POINTER pMpi3Device1DevSpecFormat_t; 4099 4100 typedef struct _MPI3_DEVICE_PAGE1 4101 { 4102 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 4103 U16 DevHandle; /* 0x08 */ 4104 U16 Reserved0A; /* 0x0A */ 4105 U16 LinkChangeCount; /* 0x0C */ 4106 U16 RateChangeCount; /* 0x0E */ 4107 U16 TMCount; /* 0x10 */ 4108 U16 Reserved12; /* 0x12 */ 4109 U32 Reserved14[10]; /* 0x14 */ 4110 U8 Reserved3C[3]; /* 0x3C */ 4111 U8 DeviceForm; /* 0x3F */ 4112 MPI3_DEVICE1_DEV_SPEC_FORMAT DeviceSpecific; /* 0x40 */ 4113 } MPI3_DEVICE_PAGE1, MPI3_POINTER PTR_MPI3_DEVICE_PAGE1, 4114 Mpi3DevicePage1_t, MPI3_POINTER pMpi3DevicePage1_t; 4115 4116 /**** Defines for the PageVersion field ****/ 4117 #define MPI3_DEVICE1_PAGEVERSION (0x00) 4118 4119 /**** Defines for the LinkChangeCount, RateChangeCount, TMCount fields ****/ 4120 #define MPI3_DEVICE1_COUNTER_MAX (0xFFFE) 4121 #define MPI3_DEVICE1_COUNTER_INVALID (0xFFFF) 4122 4123 /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ 4124 4125 #endif /* MPI30_CNFG_H */ 4126