| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 232 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const { in add() argument
233 for (const MachineOperand &MO : MOs) in add()
515 ArrayRef<MachineOperand> MOs,
533 const MCInstrDesc &MCID, bool IsIndirect, ArrayRef<MachineOperand> MOs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 585 ArrayRef<MachineOperand> MOs,
713 ArrayRef<MachineOperand> MOs,
719 ArrayRef<MachineOperand> MOs,
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| H A D | X86InstrInfo.cpp | 7181 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs, in addOperands() argument
7183 unsigned NumAddrOps = MOs.size(); in addOperands()
7188 MIB.add(MOs[i]); in addOperands()
7193 assert(MOs.size() == 5 && "Unexpected memory operand list length"); in addOperands()
7195 const MachineOperand &MO = MOs[i]; in addOperands()
7232 ArrayRef<MachineOperand> MOs, in fuseTwoAddrInst() argument
7241 addOperands(MIB, MOs); in fuseTwoAddrInst()
7261 unsigned OpNo, ArrayRef<MachineOperand> MOs, in fuseInst() argument
7274 addOperands(MIB, MOs, PtrOffset); in fuseInst()
7293 ArrayRef<MachineOperand> MOs, in makeM0Inst() argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 820 SmallVector<MachineOperand> MOs; in EmitDbgInstrRef() local
832 MOs.push_back(MachineOperand::CreateReg( in EmitDbgInstrRef()
879 MOs.push_back(GetMOForConstDbgOp(DbgOperand)); in EmitDbgInstrRef()
902 MOs.push_back(MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx)); in EmitDbgInstrRef()
907 if (MOs.size() != OpCount) in EmitDbgInstrRef()
910 return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr); in EmitDbgInstrRef()
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| H A D | FastISel.cpp | 1308 SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg( in lowerDbgValue() local
1316 TII.get(TargetOpcode::DBG_INSTR_REF), /*IsIndirect*/ false, MOs, in lowerDbgValue()
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| H A D | SelectionDAGBuilder.cpp | 6088 SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg( in EmitFuncArgumentDbgValue() local
6101 return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr); in EmitFuncArgumentDbgValue()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.cpp | 1722 SmallVector<MachineOperand, 8> MOs; in insertDebugValue() local
1724 MOs.assign(DbgValue.loc_nos().size(), in insertDebugValue()
1732 MOs.push_back(locations[LocNo]); in insertDebugValue()
1764 assert((!LocSpills[I] || MOs[I].isFI()) && in insertDebugValue()
1771 BuildMI(*MBB, I, getDebugLoc(), TII.get(DbgValueOpcode), IsIndirect, MOs, in insertDebugValue()
1776 I = findNextInsertLocation(MBB, I, StopIdx, MOs, LIS, TRI); in insertDebugValue()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | VarLocBasedImpl.cpp | 559 SmallVector<MachineOperand, 8> MOs; in BuildDbgValue() local
572 MOs.push_back(MachineOperand::CreateReg( in BuildDbgValue()
596 MOs.push_back(MachineOperand::CreateReg(Base, false)); in BuildDbgValue()
600 MOs.push_back(Orig); in BuildDbgValue()
604 MOs.push_back(Orig); in BuildDbgValue()
611 return BuildMI(MF, DbgLoc, IID, Indirect, MOs, Var, DIExpr); in BuildDbgValue()
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| H A D | InstrRefBasedImpl.cpp | 1232 SmallVector<MachineOperand> MOs; in emitLoc() local
1235 MOs.clear(); in emitLoc()
1236 MOs.assign(Properties.getLocationOpCount(), GetRegOp(0)); in emitLoc()
1237 return BuildMI(MF, DL, Desc, false, MOs, Var.getVariable(), in emitLoc()
1259 MOs.push_back(Op.MO); in emitLoc()
1360 MOs.push_back(GetRegOp(Base)); in emitLoc()
1368 MOs.push_back(GetRegOp(LocID)); in emitLoc()
1372 return BuildMI(MF, DL, Desc, Indirect, MOs, Var.getVariable(), Expr); in emitLoc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 2685 for (const auto &[Entry, MOs] : RegToMO) { in tryOptimizeAGPRPhis()
2686 if (MOs.size() == 1) in tryOptimizeAGPRPhis()
2695 const TargetRegisterClass *ARC = getRegOpRC(*MRI, *TRI, *MOs.front()); in tryOptimizeAGPRPhis()
2710 for (MachineOperand *MO : MOs) { in tryOptimizeAGPRPhis()
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