| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFixCortexA57AES1742098Pass.cpp | 101 MachineOperand *MOp; member
296 for (MachineOperand &MOp : MI.uses()) { in analyzeMF()
298 RDA.getGlobalReachingDefs(&MI, MOp.getReg(), AllDefs); in analyzeMF()
301 AESFixupLocation NewLoc{&MBB, &MI, &MOp}; in analyzeMF()
305 bool IsLiveIn = MF.front().isLiveIn(MOp.getReg()); in analyzeMF()
313 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
329 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
337 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
355 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
371 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
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| H A D | ARMTargetTransformInfo.cpp | 1140 MemOp MOp; in getNumMemOps() local
1155 MOp = MemOp::Copy(Size, /*DstAlignCanChange*/ false, DstAlign, SrcAlign, in getNumMemOps()
1169 MOp = MemOp::Set(Size, /*DstAlignCanChange*/ false, DstAlign, in getNumMemOps()
1197 MemOps, Limit, MOp, DstAddrSpace, in getNumMemOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 269 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), in tryMergeUsingCommonSlot() local
270 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { in tryMergeUsingCommonSlot()
271 if (!MOp->isReg()) in tryMergeUsingCommonSlot()
273 if (PreviousRegSeqByReg[MOp->getReg()].empty()) in tryMergeUsingCommonSlot()
275 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) { in tryMergeUsingCommonSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IndirectBranchTracking.cpp | 89 static bool IsCallReturnTwice(llvm::MachineOperand &MOp) { in IsCallReturnTwice() argument
90 if (!MOp.isGlobal()) in IsCallReturnTwice()
92 auto *CalleeFn = dyn_cast<Function>(MOp.getGlobal()); in IsCallReturnTwice()
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| H A D | X86CmovConversion.cpp | 805 for (auto &MOp : NewMI->uses()) { in convertCmovInstsToBranches() local
806 if (!MOp.isReg()) in convertCmovInstsToBranches()
808 auto It = FalseBBRegRewriteTable.find(MOp.getReg()); in convertCmovInstsToBranches()
812 MOp.setReg(It->second); in convertCmovInstsToBranches()
818 MOp.setIsKill(false); in convertCmovInstsToBranches()
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| H A D | X86FlagsCopyLowering.cpp | 172 MI.operands(), [&](MachineOperand &MOp) { in splitBlock() argument
173 return MOp.isMBB() && MOp.getMBB() == &UnsplitSucc; in splitBlock()
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| H A D | X86ISelLowering.cpp | 36471 for (auto &MOp : II.operands()) in EmitSjLjDispatchBlock() local
36472 if (MOp.isReg()) in EmitSjLjDispatchBlock()
36473 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 1831 const MachineOperand &MOp = MI->getOperand(i); in runOnMachineFunction() local
1832 if (!MOp.isReg()) in runOnMachineFunction()
1834 Register FoldAsLoadDefReg = MOp.getReg(); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 138 MachineOperand &MOp = MI.getOperand(NumOp); in foldConstantsIntoIntrinsics() local
139 MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg()); in foldConstantsIntoIntrinsics()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2651 for (auto &MOp : II.operands()) in emitSjLjDispatchBlock() local
2652 if (MOp.isReg()) in emitSjLjDispatchBlock()
2653 DefRegs[MOp.getReg()] = true; in emitSjLjDispatchBlock()
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