| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeVGPRLiveRange.cpp | 238 Register MOReg = MO.getReg(); in collectCandidateRegisters() local
240 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectCandidateRegisters()
244 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
245 const MachineBasicBlock *DefMBB = MRI->getVRegDef(MOReg)->getParent(); in collectCandidateRegisters()
253 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
254 if (!VI.isLiveIn(*Endif, MOReg, *MRI)) { in collectCandidateRegisters()
255 KillsInElse.insert(MOReg); in collectCandidateRegisters()
257 LLVM_DEBUG(dbgs() << "Excluding " << printReg(MOReg, TRI) in collectCandidateRegisters()
364 Register MOReg = MO.getReg(); in collectWaterfallCandidateRegisters() local
366 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectWaterfallCandidateRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 112 Register MOReg = MO.getReg(); in addUsedLanesOnOperand() local
113 if (!MOReg.isVirtual()) in addUsedLanesOnOperand()
119 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand()
121 unsigned MORegIdx = Register::virtReg2Index(MOReg); in addUsedLanesOnOperand()
296 Register MOReg = MO.getReg(); in determineInitialDefinedLanes() local
297 if (!MOReg) in determineInitialDefinedLanes()
301 if (MOReg.isPhysical()) { in determineInitialDefinedLanes()
306 assert(MOReg.isVirtual()); in determineInitialDefinedLanes()
307 if (MRI->hasOneDef(MOReg)) { in determineInitialDefinedLanes()
308 const MachineOperand &MODef = *MRI->def_begin(MOReg); in determineInitialDefinedLanes()
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| H A D | TwoAddressInstructionPass.cpp | 964 Register MOReg = MO.getReg(); in rescheduleMIBelowKill() local
965 if (!MOReg) in rescheduleMIBelowKill()
968 Defs.push_back(MOReg); in rescheduleMIBelowKill()
970 Uses.push_back(MOReg); in rescheduleMIBelowKill()
971 if (MOReg != Reg && isPlainlyKilled(MO)) in rescheduleMIBelowKill()
972 Kills.push_back(MOReg); in rescheduleMIBelowKill()
1007 Register MOReg = MO.getReg(); in rescheduleMIBelowKill() local
1008 if (!MOReg) in rescheduleMIBelowKill()
1011 if (regOverlapsSet(Uses, MOReg)) in rescheduleMIBelowKill()
1014 if (!MO.isDead() && regOverlapsSet(Defs, MOReg)) in rescheduleMIBelowKill()
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| H A D | LiveVariables.cpp | 536 Register MOReg = MO.getReg(); in runOnInstr() local
538 if (!(MOReg.isPhysical() && MRI->isReserved(MOReg))) in runOnInstr()
541 UseRegs.push_back(MOReg); in runOnInstr()
546 if (MOReg.isPhysical() && !MRI->isReserved(MOReg)) in runOnInstr()
548 DefRegs.push_back(MOReg); in runOnInstr()
554 for (unsigned MOReg : UseRegs) { in runOnInstr() local
555 if (Register::isVirtualRegister(MOReg)) in runOnInstr()
556 HandleVirtRegUse(MOReg, MBB, MI); in runOnInstr()
557 else if (!MRI->isReserved(MOReg)) in runOnInstr()
558 HandlePhysRegUse(MOReg, MI); in runOnInstr()
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| H A D | MachineInstrBundle.cpp | 349 Register MOReg = MO.getReg(); in AnalyzePhysRegInBundle() local
350 if (!MOReg || !MOReg.isPhysical()) in AnalyzePhysRegInBundle()
353 if (!TRI->regsOverlap(MOReg, Reg)) in AnalyzePhysRegInBundle()
356 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in AnalyzePhysRegInBundle()
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| H A D | MachineInstr.cpp | 1061 Register MOReg = MO.getReg(); in findRegisterUseOperandIdx() local
1062 if (!MOReg) in findRegisterUseOperandIdx()
1064 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) in findRegisterUseOperandIdx()
1115 Register MOReg = MO.getReg(); in findRegisterDefOperandIdx() local
1116 bool Found = (MOReg == Reg); in findRegisterDefOperandIdx()
1117 if (!Found && TRI && isPhys && MOReg.isPhysical()) { in findRegisterDefOperandIdx()
1119 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1121 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
2087 Register MOReg = MO.getReg(); in addRegisterDead() local
2088 if (!MOReg) in addRegisterDead()
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| H A D | TargetInstrInfo.cpp | 1665 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs() local
1666 if (MOReg.isUndef()) in getRegSequenceInputs()
1672 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1690 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs() local
1691 if (MOReg.isUndef()) in getExtractSubregInputs()
1697 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1698 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
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| H A D | MachineCSE.cpp | 393 Register MOReg = MO.getReg(); in PhysRegDefsReach() local
394 if (MOReg.isVirtual()) in PhysRegDefsReach()
396 if (PhysRefs.count(MOReg.asMCReg())) in PhysRegDefsReach()
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| H A D | MachineLICM.cpp | 1170 Register MOReg = MO.getReg(); in HasHighOperandLatency() local
1171 if (MOReg != Reg) in HasHighOperandLatency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 392 Register MOReg = MO.getReg(); in PrintAsmOperand() local
395 if (!SP::IntPairRegClass.contains(MOReg)) { in PrintAsmOperand()
400 MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even, in PrintAsmOperand()
402 if (!MOReg) { in PrintAsmOperand()
414 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); in PrintAsmOperand()
415 LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 204 Register MOReg = MO.getReg(); in processBlock() local
205 if (RegInfo.hasOneDef(MOReg)) { in processBlock()
207 RegInfo.getOneDef(MOReg)->getParent(); in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 565 Register MOReg = MO.getReg(); in restoreLatency() local
567 IsSameOrSubReg = (MOReg == DepR); in restoreLatency()
569 IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); in restoreLatency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 143 if (Register MOReg = MO.getReg()) { in getRegReferences() local
144 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 5465 const MachineOperand *MOReg = &MI.getOperand(1); in getRegSequenceLikeInputs() local
5466 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5467 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5468 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5470 MOReg = &MI.getOperand(2); in getRegSequenceLikeInputs()
5471 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5472 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5473 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5491 const MachineOperand &MOReg = MI.getOperand(2); in getExtractSubregLikeInputs() local
5492 if (MOReg.isUndef()) in getExtractSubregLikeInputs()
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