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Searched refs:MOReg (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeVGPRLiveRange.cpp245 Register MOReg = MO.getReg(); in collectCandidateRegisters() local
247 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectCandidateRegisters()
251 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
252 const MachineBasicBlock *DefMBB = MRI->getVRegDef(MOReg)->getParent(); in collectCandidateRegisters()
260 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
261 if (!VI.isLiveIn(*Endif, MOReg, *MRI)) { in collectCandidateRegisters()
262 KillsInElse.insert(MOReg); in collectCandidateRegisters()
264 LLVM_DEBUG(dbgs() << "Excluding " << printReg(MOReg, TRI) in collectCandidateRegisters()
371 Register MOReg = MO.getReg(); in collectWaterfallCandidateRegisters() local
373 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectWaterfallCandidateRegisters()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp112 Register MOReg = MO.getReg(); in addUsedLanesOnOperand() local
113 if (!MOReg.isVirtual()) in addUsedLanesOnOperand()
119 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand()
121 unsigned MORegIdx = MOReg.virtRegIndex(); in addUsedLanesOnOperand()
296 Register MOReg = MO.getReg(); in determineInitialDefinedLanes() local
297 if (!MOReg) in determineInitialDefinedLanes()
301 if (MOReg.isPhysical()) { in determineInitialDefinedLanes()
306 assert(MOReg.isVirtual()); in determineInitialDefinedLanes()
307 if (MRI->hasOneDef(MOReg)) { in determineInitialDefinedLanes()
308 const MachineOperand &MODef = *MRI->def_begin(MOReg); in determineInitialDefinedLanes()
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H A DTwoAddressInstructionPass.cpp966 Register MOReg = MO.getReg(); in rescheduleMIBelowKill() local
967 if (!MOReg) in rescheduleMIBelowKill()
970 Defs.push_back(MOReg); in rescheduleMIBelowKill()
972 Uses.push_back(MOReg); in rescheduleMIBelowKill()
973 if (MOReg != Reg && isPlainlyKilled(MO)) in rescheduleMIBelowKill()
974 Kills.push_back(MOReg); in rescheduleMIBelowKill()
1009 Register MOReg = MO.getReg(); in rescheduleMIBelowKill() local
1010 if (!MOReg) in rescheduleMIBelowKill()
1013 if (regOverlapsSet(Uses, MOReg)) in rescheduleMIBelowKill()
1016 if (!MO.isDead() && regOverlapsSet(Defs, MOReg)) in rescheduleMIBelowKill()
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H A DLiveVariables.cpp529 Register MOReg = MO.getReg(); in runOnInstr() local
531 if (!(MOReg.isPhysical() && MRI->isReserved(MOReg))) in runOnInstr()
534 UseRegs.push_back(MOReg); in runOnInstr()
539 if (MOReg.isPhysical() && !MRI->isReserved(MOReg)) in runOnInstr()
541 DefRegs.push_back(MOReg); in runOnInstr()
547 for (Register MOReg : UseRegs) { in runOnInstr() local
548 if (MOReg.isVirtual()) in runOnInstr()
549 HandleVirtRegUse(MOReg, MBB, MI); in runOnInstr()
550 else if (!MRI->isReserved(MOReg)) in runOnInstr()
551 HandlePhysRegUse(MOReg, MI); in runOnInstr()
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H A DMachineInstrBundle.cpp329 Register MOReg = MO.getReg(); in AnalyzePhysRegInBundle() local
330 if (!MOReg || !MOReg.isPhysical()) in AnalyzePhysRegInBundle()
333 if (!TRI->regsOverlap(MOReg, Reg)) in AnalyzePhysRegInBundle()
336 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in AnalyzePhysRegInBundle()
H A DMachineInstr.cpp1088 Register MOReg = MO.getReg(); in findRegisterUseOperandIdx() local
1089 if (!MOReg) in findRegisterUseOperandIdx()
1091 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) in findRegisterUseOperandIdx()
1142 Register MOReg = MO.getReg(); in findRegisterDefOperandIdx() local
1143 bool Found = (MOReg == Reg); in findRegisterDefOperandIdx()
1144 if (!Found && TRI && isPhys && MOReg.isPhysical()) { in findRegisterDefOperandIdx()
1146 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1148 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
2201 Register MOReg = MO.getReg(); in addRegisterDead() local
2202 if (!MOReg) in addRegisterDead()
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H A DTargetInstrInfo.cpp1975 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs() local
1976 if (MOReg.isUndef()) in getRegSequenceInputs()
1982 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
2000 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs() local
2001 if (MOReg.isUndef()) in getExtractSubregInputs()
2007 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
2008 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
H A DMachineCSE.cpp386 Register MOReg = MO.getReg(); in PhysRegDefsReach() local
387 if (MOReg.isVirtual()) in PhysRegDefsReach()
389 if (PhysRefs.count(MOReg.asMCReg())) in PhysRegDefsReach()
H A DMachineLICM.cpp1194 Register MOReg = MO.getReg(); in HasHighOperandLatency() local
1195 if (MOReg != Reg) in HasHighOperandLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp441 Register MOReg = MO.getReg(); in PrintAsmOperand() local
444 if (!SP::IntPairRegClass.contains(MOReg)) { in PrintAsmOperand()
449 MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even, in PrintAsmOperand()
451 if (!MOReg) { in PrintAsmOperand()
463 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); in PrintAsmOperand()
464 LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd); in PrintAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTLSDynamicCall.cpp200 Register MOReg = MO.getReg(); in processBlock() local
201 if (RegInfo.hasOneDef(MOReg)) { in processBlock()
203 RegInfo.getOneDef(MOReg)->getParent(); in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp566 Register MOReg = MO.getReg(); in restoreLatency() local
568 IsSameOrSubReg = (MOReg == DepR); in restoreLatency()
570 IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); in restoreLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp140 if (Register MOReg = MO.getReg()) { in getRegReferences() local
141 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp5312 const MachineOperand *MOReg = &MI.getOperand(1); in getRegSequenceLikeInputs() local
5313 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5314 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5315 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5317 MOReg = &MI.getOperand(2); in getRegSequenceLikeInputs()
5318 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5319 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5320 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5338 const MachineOperand &MOReg = MI.getOperand(2); in getExtractSubregLikeInputs() local
5339 if (MOReg.isUndef()) in getExtractSubregLikeInputs()
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