| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 131 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
144 printRegName(O, MO2.getReg()); in printInst()
154 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
156 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
165 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
172 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
430 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
442 printRegName(O, MO2.getReg()); in printSORegRegOperand()
450 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
455 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
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| H A D | ARMMCTargetDesc.cpp | 446 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode_i12() local
447 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode_i12()
450 int32_t OffImm = (int32_t)MO2.getImm(); in evaluateMemOpAddrForAddrMode_i12()
464 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode3() local
466 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) in evaluateMemOpAddrForAddrMode3()
484 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode5() local
485 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5()
488 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); in evaluateMemOpAddrForAddrMode5()
489 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); in evaluateMemOpAddrForAddrMode5()
503 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode5FP16() local
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| H A D | ARMMCCodeEmitter.cpp | 921 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
923 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1275 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getHiLoImmOpValue()
1278 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getHiLoImmOpValue()
1279 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1280 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1369 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1384 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1532 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue()
1533 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2 in getSORegRegOpValue()
932 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); getThumbAddrModeRegRegOpValue() local
1286 const MCOperand &MO2 = MI.getOperand(OpIdx+2); getLdStSORegOpValue() local
1380 const MCOperand &MO2 = MI.getOperand(OpIdx+2); getAddrMode3OpValue() local
1543 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); getSORegRegOpValue() local
1627 const MCOperand &MO2 = MI.getOperand(OpNum+1); getT2AddrModeSORegOpValue() local
1647 const MCOperand &MO2 = MI.getOperand(OpNum+1); getT2AddrModeImmOpValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 68 const MachineOperand &MO2);
73 const MachineOperand &MO2);
202 const MachineOperand &MO2) { in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical()); in isIdenticalOp()
214 const MachineOperand &MO2) { in isSimilarDispOp() argument
215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
217 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
219 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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| H A D | X86RegisterInfo.cpp | 1066 MachineOperand &MO2 = MI->getOperand(2); in getTileShape() local
1067 ShapeT Shape(&MO1, &MO2, MRI); in getTileShape()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCCodeEmitter.cpp | 129 const MCOperand &MO2 = MI.getOperand(Op + 1); in getMemOpValue()
130 if (MO2.isImm()) { in getMemOpValue()
132 return ((unsigned)MO2.getImm() << 4) | Reg; in getMemOpValue()
135 assert(MO2.isExpr() && "Expr operand expected"); in getMemOpValue()
148 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(), in getMemOpValue()
128 const MCOperand &MO2 = MI.getOperand(Op + 1); getMemOpValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandPseudoInsts.cpp | 509 unsigned MO0, MO1, MO2, MO3; in expandLargeAddressLoad() local
516 MO2 = LoongArchII::MO_PCREL64_LO; in expandLargeAddressLoad()
525 MO2 = LoongArchII::MO_GOT_PC64_LO; in expandLargeAddressLoad()
531 MO2 = LoongArchII::MO_IE_PC64_LO; in expandLargeAddressLoad()
559 Part2.addExternalSymbol(SymName, MO2); in expandLargeAddressLoad()
564 Part2.addDisp(Symbol, 0, MO2); in expandLargeAddressLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1289 MCOperand &MO2) { in makeCombineInst() argument
1294 TmpInst.addOperand(MO2); in makeCombineInst()
1651 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1653 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1658 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1672 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1673 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 923 MachineOperand &MO2 = Cond[2]; in reverseBranchCondition() local
924 switch (MO2.getReg()) { in reverseBranchCondition()
926 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
929 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
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| H A D | SIInstrInfo.cpp | 532 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr() local
533 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
537 auto Base2 = MO2->getValue(); in memOpsHaveSameBasePtr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 455 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
456 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 1210 for (const MachineOperand &MO2 : MI.all_defs()) { in collectVRegUses() local
1211 if (MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2671 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
2672 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
2676 auto Base2 = MO2->getValue(); in memOpsHaveSameBasePtr()
2664 auto MO2 = *MI2.memoperands_begin(); memOpsHaveSameBasePtr() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 733 for (auto MO2 : DefMI->uses()) in getConstantFromConstantPool() local
734 if (MO2.isCPI()) in getConstantFromConstantPool()
735 return (MCP->getConstants())[MO2.getIndex()].Val.ConstVal; in getConstantFromConstantPool()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1628 MachineOperand &MO2 = MI.getOperand(0); in narrowScalar() local
1631 MIRBuilder.buildSExt(MO2, DstExt); in narrowScalar()
1632 MO2.setReg(DstExt); in narrowScalar()
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