| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 129 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
142 printRegName(O, MO2.getReg()); in printInst()
152 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
154 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
163 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
170 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
428 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
440 printRegName(O, MO2.getReg()); in printSORegRegOperand()
448 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
453 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
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| H A D | ARMMCTargetDesc.cpp | 451 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode_i12() local
452 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode_i12()
455 int32_t OffImm = (int32_t)MO2.getImm(); in evaluateMemOpAddrForAddrMode_i12()
469 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode3() local
471 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) in evaluateMemOpAddrForAddrMode3()
489 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode5() local
490 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5()
493 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); in evaluateMemOpAddrForAddrMode5()
494 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); in evaluateMemOpAddrForAddrMode5()
508 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); in evaluateMemOpAddrForAddrMode5FP16() local
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| H A D | ARMMCCodeEmitter.cpp | 928 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
930 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1282 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1285 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1286 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1287 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1376 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1391 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1576 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1577 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 68 const MachineOperand &MO2);
73 const MachineOperand &MO2);
202 const MachineOperand &MO2) { in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical()); in isIdenticalOp()
214 const MachineOperand &MO2) { in isSimilarDispOp() argument
215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
217 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
219 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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| H A D | X86RegisterInfo.cpp | 1095 MachineOperand &MO2 = MI->getOperand(2); in getTileShape() local
1096 ShapeT Shape(&MO1, &MO2, MRI); in getTileShape()
1109 MachineOperand &MO2 = MI->getOperand(2); in getTileShape() local
1111 ShapeT Shape({&MO1, &MO2, &MO1, &MO3}, MRI); in getTileShape()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCCodeEmitter.cpp | 140 const MCOperand &MO2 = MI.getOperand(Op + 1); in getMemOpValue() local
141 if (MO2.isImm()) { in getMemOpValue()
143 return ((unsigned)MO2.getImm() << 4) | Reg; in getMemOpValue()
146 assert(MO2.isExpr() && "Expr operand expected"); in getMemOpValue()
159 addFixup(Fixups, Offset, MO2.getExpr(), FixupKind); in getMemOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.cpp | 426 auto MO2 = Lu32I->getOperand(2).getTargetFlags(); in isSafeToMove() local
428 MO2 == LoongArchII::MO_PCREL64_LO) in isSafeToMove()
432 MO1 == LoongArchII::MO_GOT_PC_LO && MO2 == LoongArchII::MO_GOT_PC64_LO) in isSafeToMove()
435 MO2 == LoongArchII::MO_IE_PC64_LO) in isSafeToMove()
439 MO2 == LoongArchII::MO_DESC64_PC_LO) in isSafeToMove()
485 auto MO2 = LoongArchII::getDirectFlags(Ld->getOperand(2)); in isSafeToMove() local
486 if (MO1 == LoongArchII::MO_DESC_PC_LO && MO2 == LoongArchII::MO_DESC_LD) in isSafeToMove()
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| H A D | LoongArchExpandPseudoInsts.cpp | 234 unsigned MO0, MO1, MO2, MO3; in expandLargeAddressLoad() local
241 MO2 = LoongArchII::MO_PCREL64_LO; in expandLargeAddressLoad()
250 MO2 = LoongArchII::MO_GOT_PC64_LO; in expandLargeAddressLoad()
256 MO2 = LoongArchII::MO_IE_PC64_LO; in expandLargeAddressLoad()
299 Part2.addExternalSymbol(SymName, MO2); in expandLargeAddressLoad()
304 Part2.addDisp(Symbol, 0, MO2); in expandLargeAddressLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1296 MCOperand &MO2) { in makeCombineInst() argument
1301 TmpInst.addOperand(MO2); in makeCombineInst()
1660 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1662 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1667 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1681 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1682 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 913 MachineOperand &MO2 = Cond[2]; in reverseBranchCondition() local
914 switch (MO2.getReg()) { in reverseBranchCondition()
916 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
919 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
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| H A D | SIInstrInfo.cpp | 542 auto *MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr() local
543 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
547 const auto *Base2 = MO2->getValue(); in memOpsHaveSameBasePtr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 453 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
454 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 1450 for (const MachineOperand &MO2 : MI.all_defs()) { in collectVRegUses() local
1451 if (MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3215 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr() local
3216 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
3220 auto Base2 = MO2->getValue(); in memOpsHaveSameBasePtr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 731 for (auto MO2 : DefMI->uses()) in getConstantFromConstantPool() local
732 if (MO2.isCPI()) in getConstantFromConstantPool()
733 return (MCP->getConstants())[MO2.getIndex()].Val.ConstVal; in getConstantFromConstantPool()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1926 MachineOperand &MO2 = MI.getOperand(0); in narrowScalar() local
1929 MIRBuilder.buildSExt(MO2, DstExt); in narrowScalar()
1930 MO2.setReg(DstExt); in narrowScalar()
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