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Searched refs:MO1 (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp130 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
141 printRegName(O, MO1.getReg()); in printInst()
153 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
163 printRegName(O, MO1.getReg()); in printInst()
398 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local
399 if (MO1.isExpr()) { in printThumbLdrLabelOperand()
400 MO1.getExpr()->print(O, &MAI); in printThumbLdrLabelOperand()
407 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
429 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand() local
433 printRegName(O, MO1.getReg()); in printSORegRegOperand()
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H A DARMMCCodeEmitter.cpp585 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getMachineOpValue()
589 int32_t SImm = MO1.getImm();
920 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAdrLabelOpValue()
922 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
975 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddrModeImm12OpValue()
976 if (MO1.isImm()) { in getAddrModeImm12OpValue()
978 } else if (MO1.isExpr()) { in getAddrModeImm12OpValue()
984 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc())); in getAddrModeImm12OpValue()
1176 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm7s4OpValue()
1178 unsigned Imm8 = MO1
596 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); EncodeAddrModeOpValues() local
931 const MCOperand &MO1 = MI.getOperand(OpIdx); getThumbAddrModeRegRegOpValue() local
986 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddrModeImm12OpValue() local
1187 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getT2AddrModeImm0_1020s4OpValue() local
1285 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getLdStSORegOpValue() local
1322 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getAddrMode2OffsetOpValue() local
1344 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getPostIdxRegOpValue() local
1358 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getAddrMode3OffsetOpValue() local
1379 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getAddrMode3OpValue() local
1412 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddrModeThumbSPOpValue() local
1430 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddrModeISOpValue() local
1542 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getSORegRegOpValue() local
1588 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getSORegImmOpValue() local
1626 const MCOperand &MO1 = MI.getOperand(OpNum); getT2AddrModeSORegOpValue() local
1646 const MCOperand &MO1 = MI.getOperand(OpNum); getT2AddrModeImmOpValue() local
1671 const MCOperand &MO1 = MI.getOperand(OpNum); getT2AddrModeImm8OffsetOpValue() local
1697 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getT2SORegOpValue() local
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H A DARMMCTargetDesc.cpp445 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode_i12() local
447 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode_i12()
463 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode3() local
466 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) in evaluateMemOpAddrForAddrMode3()
483 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode5() local
485 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5()
502 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode5FP16() local
504 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5FP16()
522 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrModeT2_i8s4() local
524 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrModeT2_i8s4()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp67 static inline bool isIdenticalOp(const MachineOperand &MO1,
72 static bool isSimilarDispOp(const MachineOperand &MO1,
201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical()); in isIdenticalOp()
213 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument
215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
217 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
219 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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H A DX86RegisterInfo.cpp1065 MachineOperand &MO1 = MI->getOperand(1); in getTileShape() local
1067 ShapeT Shape(&MO1, &MO2, MRI); in getTileShape()
H A DX86FloatingPoint.cpp1527 const MachineOperand &MO1 = MI.getOperand(1); in handleSpecialFP() local
1529 bool KillsSrc = MI.killsRegister(MO1.getReg(), /*TRI=*/nullptr); in handleSpecialFP()
1533 unsigned SrcFP = getFPReg(MO1); in handleSpecialFP()
H A DX86InstrInfo.cpp8454 MachineOperand &MO1 = DataMI->getOperand(1); in unfoldMemoryOperand() local
8455 if (MO1.isImm() && MO1.getImm() == 0) { in unfoldMemoryOperand()
8474 MO1.ChangeToRegister(MO0.getReg(), false); in unfoldMemoryOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp125 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue()
126 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue()
127 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
124 const MCOperand &MO1 = MI.getOperand(Op); getMemOpValue() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp1298 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
1299 unsigned Flags = MO1.getTargetFlags(); in expandMI()
1306 if (MO1.isGlobal()) { in expandMI()
1307 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags); in expandMI()
1308 } else if (MO1.isSymbol()) { in expandMI()
1309 MIB.addExternalSymbol(MO1.getSymbolName(), Flags); in expandMI()
1311 assert(MO1.isCPI() && in expandMI()
1313 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags); in expandMI()
1338 if (MO1.isGlobal()) { in expandMI()
1339 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE); in expandMI()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp202 auto MO1 = *L1->memoperands().begin(); in getHazardType() local
203 auto BaseVal1 = MO1->getValue(); in getHazardType()
204 auto BasePseudoVal1 = MO1->getPseudoValue(); in getHazardType()
H A DARMAsmPrinter.cpp995 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableAddrs() local
996 unsigned JTI = MO1.getIndex(); in emitJumpTableAddrs()
1041 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableInsts() local
1042 unsigned JTI = MO1.getIndex(); in emitJumpTableInsts()
1071 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableTBInst() local
1072 unsigned JTI = MO1.getIndex(); in emitJumpTableTBInst()
H A DARMExpandPseudoInsts.cpp2645 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2646 auto Flags = MO1.getTargetFlags(); in ExpandMI()
2647 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI()
2706 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2707 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI()
2708 unsigned TF = MO1.getTargetFlags(); in ExpandMI()
2718 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) in ExpandMI()
2724 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) in ExpandMI()
H A DARMBaseInstrInfo.cpp1877 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue() local
1878 if (MO0.getOffset() != MO1.getOffset()) in produceSameValue()
1886 return MO0.getGlobal() == MO1.getGlobal(); in produceSameValue()
1891 int CPI1 = MO1.getIndex(); in produceSameValue()
1930 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue() local
1931 if (!MO0.isIdenticalTo(MO1)) in produceSameValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp273 const MCOperand &MO1 = MI->getOperand(OpNo + 1); in printRegReg() local
274 assert(MO1.isReg() && "printRegReg can only print register operands"); in printRegReg()
275 printRegName(O, MO1.getReg()); in printRegReg()
H A DRISCVMCCodeEmitter.cpp566 const MCOperand &MO1 = MI.getOperand(OpNo + 1); in getRegReg() local
567 assert(MO.isReg() && MO1.isReg() && "Expected registers."); in getRegReg()
570 unsigned Op1 = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getRegReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandPseudoInsts.cpp509 unsigned MO0, MO1, MO2, MO3; in expandLargeAddressLoad() local
515 MO1 = LoongArchII::MO_PCREL_HI; in expandLargeAddressLoad()
524 MO1 = IdentifyingMO; in expandLargeAddressLoad()
530 MO1 = LoongArchII::MO_IE_PC_HI; in expandLargeAddressLoad()
558 Part1.addExternalSymbol(SymName, MO1); in expandLargeAddressLoad()
563 Part1.addDisp(Symbol, 0, MO1); in expandLargeAddressLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocFast.cpp1338 const MachineOperand &MO1 = MI.getOperand(I1); in findAndSortDefOperandIndexes() local
1340 Register Reg1 = MO1.getReg(); in findAndSortDefOperandIndexes()
1359 bool Livethrough1 = MO1.isEarlyClobber() || MO1.isTied() || in findAndSortDefOperandIndexes()
1360 (MO1.getSubReg() == 0 && !MO1.isUndef()); in findAndSortDefOperandIndexes()
H A DMachineVerifier.cpp3212 const MachineOperand &MO1 = Phi.getOperand(I + 1); in checkPHIOps() local
3213 if (!MO1.isMBB()) { in checkPHIOps()
3214 report("Expected PHI operand to be a basic block", &MO1, I + 1); in checkPHIOps()
3218 const MachineBasicBlock &Pre = *MO1.getMBB(); in checkPHIOps()
3220 report("PHI input is not a predecessor block", &MO1, I + 1); in checkPHIOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp286 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue()
287 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
289 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
280 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddSubImmOpValue() local
H A DAArch64InstPrinter.cpp1427 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1430 if (MO1.isImm()) { in printRPRFMOperand()
1432 markup(O, Markup::Immediate) << "#" << formatImm(MO1.getImm() * Scale); in printRPRFMOperand()
1434 assert(MO1.isExpr() && "Unexpected operand type!"); in printRPRFMOperand()
1436 MO1.getExpr()->print(O, &MAI); in printRPRFMOperand()
1414 const MCOperand MO1 = MI->getOperand(OpNum + 1); printAMIndexedWB() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1288 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst() argument
1293 TmpInst.addOperand(MO1); in makeCombineInst()
1650 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1658 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1665 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1667 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1673 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp465 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
466 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
467 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp2670 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr()
2672 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
2675 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr()
2663 auto MO1 = *MI1.memoperands_begin(); memOpsHaveSameBasePtr() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1624 MachineOperand &MO1 = MI.getOperand(1); in narrowScalar() local
1625 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); in narrowScalar()
1626 MO1.setReg(TruncMIB.getReg(0)); in narrowScalar()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp531 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr() local
533 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
536 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr()