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Searched refs:MO1 (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp67 static inline bool isIdenticalOp(const MachineOperand &MO1,
72 static bool isSimilarDispOp(const MachineOperand &MO1,
201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical()); in isIdenticalOp()
213 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument
215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
217 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
219 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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H A DX86RegisterInfo.cpp1094 MachineOperand &MO1 = MI->getOperand(1); in getTileShape() local
1096 ShapeT Shape(&MO1, &MO2, MRI); in getTileShape()
1108 MachineOperand &MO1 = MI->getOperand(1); in getTileShape() local
1111 ShapeT Shape({&MO1, &MO2, &MO1, &MO3}, MRI); in getTileShape()
H A DX86FloatingPoint.cpp1544 const MachineOperand &MO1 = MI.getOperand(1); in handleSpecialFP() local
1546 bool KillsSrc = MI.killsRegister(MO1.getReg(), /*TRI=*/nullptr); in handleSpecialFP()
1550 unsigned SrcFP = getFPReg(MO1); in handleSpecialFP()
H A DX86InstrInfo.cpp8549 MachineOperand &MO1 = DataMI->getOperand(1); in unfoldMemoryOperand() local
8550 if (MO1.isImm() && MO1.getImm() == 0) { in unfoldMemoryOperand()
8569 MO1.ChangeToRegister(MO0.getReg(), false); in unfoldMemoryOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp128 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
139 printRegName(O, MO1.getReg()); in printInst()
151 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
161 printRegName(O, MO1.getReg()); in printInst()
396 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local
397 if (MO1.isExpr()) { in printThumbLdrLabelOperand()
398 MAI.printExpr(O, *MO1.getExpr()); in printThumbLdrLabelOperand()
405 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
427 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand() local
431 printRegName(O, MO1.getReg()); in printSORegRegOperand()
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H A DARMMCCodeEmitter.cpp592 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues() local
596 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
927 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAddrModeRegRegOpValue() local
929 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
982 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddrModeImm12OpValue() local
983 if (MO1.isImm()) { in getAddrModeImm12OpValue()
985 } else if (MO1.isExpr()) { in getAddrModeImm12OpValue()
991 addFixup(Fixups, 0, MO1.getExpr(), Kind); in getAddrModeImm12OpValue()
1183 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm0_1020s4OpValue() local
1185 unsigned Imm8 = MO1.getImm(); in getT2AddrModeImm0_1020s4OpValue()
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H A DARMMCTargetDesc.cpp450 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode_i12() local
452 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode_i12()
468 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode3() local
471 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) in evaluateMemOpAddrForAddrMode3()
488 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode5() local
490 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5()
507 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode5FP16() local
509 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5FP16()
527 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrModeT2_i8s4() local
529 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrModeT2_i8s4()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp425 auto MO1 = AddI->getOperand(2).getTargetFlags(); in isSafeToMove() local
427 if (MO0 == LoongArchII::MO_PCREL_HI && MO1 == LoongArchII::MO_PCREL_LO && in isSafeToMove()
432 MO1 == LoongArchII::MO_GOT_PC_LO && MO2 == LoongArchII::MO_GOT_PC64_LO) in isSafeToMove()
434 if (MO0 == LoongArchII::MO_IE_PC_HI && MO1 == LoongArchII::MO_IE_PC_LO && in isSafeToMove()
438 MO1 == LoongArchII::MO_DESC_PC_LO && in isSafeToMove()
484 auto MO1 = LoongArchII::getDirectFlags(SecondOp->getOperand(2)); in isSafeToMove() local
486 if (MO1 == LoongArchII::MO_DESC_PC_LO && MO2 == LoongArchII::MO_DESC_LD) in isSafeToMove()
493 auto MO1 = LoongArchII::getDirectFlags(SecondOp->getOperand(2)); in isSafeToMove() local
495 MO1 == LoongArchII::MO_PCREL_LO) in isSafeToMove()
498 MO1 == LoongArchII::MO_GOT_PC_LO) in isSafeToMove()
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H A DLoongArchExpandPseudoInsts.cpp234 unsigned MO0, MO1, MO2, MO3; in expandLargeAddressLoad() local
240 MO1 = LoongArchII::MO_PCREL_HI; in expandLargeAddressLoad()
249 MO1 = IdentifyingMO; in expandLargeAddressLoad()
255 MO1 = LoongArchII::MO_IE_PC_HI; in expandLargeAddressLoad()
298 Part1.addExternalSymbol(SymName, MO1); in expandLargeAddressLoad()
303 Part1.addDisp(Symbol, 0, MO1); in expandLargeAddressLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp136 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue() local
137 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue()
138 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp1326 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
1327 unsigned Flags = MO1.getTargetFlags(); in expandMI()
1334 if (MO1.isGlobal()) { in expandMI()
1335 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags); in expandMI()
1336 } else if (MO1.isSymbol()) { in expandMI()
1337 MIB.addExternalSymbol(MO1.getSymbolName(), Flags); in expandMI()
1339 assert(MO1.isCPI() && in expandMI()
1341 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags); in expandMI()
1366 if (MO1.isGlobal()) { in expandMI()
1367 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE); in expandMI()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp200 auto MO1 = *L1->memoperands().begin(); in getHazardType() local
201 auto BaseVal1 = MO1->getValue(); in getHazardType()
202 auto BasePseudoVal1 = MO1->getPseudoValue(); in getHazardType()
H A DARMAsmPrinter.cpp1002 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableAddrs() local
1003 unsigned JTI = MO1.getIndex(); in emitJumpTableAddrs()
1048 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableInsts() local
1049 unsigned JTI = MO1.getIndex(); in emitJumpTableInsts()
1078 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableTBInst() local
1079 unsigned JTI = MO1.getIndex(); in emitJumpTableTBInst()
H A DARMExpandPseudoInsts.cpp2687 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2688 auto Flags = MO1.getTargetFlags(); in ExpandMI()
2689 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI()
2748 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2749 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI()
2750 unsigned TF = MO1.getTargetFlags(); in ExpandMI()
2760 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) in ExpandMI()
2766 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) in ExpandMI()
H A DARMBaseInstrInfo.cpp1720 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue() local
1721 if (MO0.getOffset() != MO1.getOffset()) in produceSameValue()
1729 return MO0.getGlobal() == MO1.getGlobal(); in produceSameValue()
1734 int CPI1 = MO1.getIndex(); in produceSameValue()
1773 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue() local
1774 if (!MO0.isIdenticalTo(MO1)) in produceSameValue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocFast.cpp1403 const MachineOperand &MO1 = MI.getOperand(I1); in findAndSortDefOperandIndexes() local
1405 Register Reg1 = MO1.getReg(); in findAndSortDefOperandIndexes()
1424 bool Livethrough1 = MO1.isEarlyClobber() || MO1.isTied() || in findAndSortDefOperandIndexes()
1425 (MO1.getSubReg() == 0 && !MO1.isUndef()); in findAndSortDefOperandIndexes()
H A DMachineVerifier.cpp3365 const MachineOperand &MO1 = Phi.getOperand(I + 1); in checkPHIOps() local
3366 if (!MO1.isMBB()) { in checkPHIOps()
3367 report("Expected PHI operand to be a basic block", &MO1, I + 1); in checkPHIOps()
3371 const MachineBasicBlock &Pre = *MO1.getMBB(); in checkPHIOps()
3373 report("PHI input is not a predecessor block", &MO1, I + 1); in checkPHIOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp294 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local
295 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
297 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
H A DAArch64InstPrinter.cpp1440 const MCOperand MO1 = MI->getOperand(OpNum + 1); in printAMIndexedWB() local
1443 if (MO1.isImm()) { in printAMIndexedWB()
1445 markup(O, Markup::Immediate) << "#" << formatImm(MO1.getImm() * Scale); in printAMIndexedWB()
1447 assert(MO1.isExpr() && "Unexpected operand type!"); in printAMIndexedWB()
1449 MAI.printExpr(O, *MO1.getExpr()); in printAMIndexedWB()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1295 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst() argument
1300 TmpInst.addOperand(MO1); in makeCombineInst()
1659 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1667 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1674 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1676 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1682 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp463 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
464 MCRegister High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
465 MCRegister Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp541 auto *MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr() local
543 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
546 const auto *Base1 = MO1->getValue(); in memOpsHaveSameBasePtr()
2788 const MachineOperand *MO1) const { in isLegalToSwap()
2808 if ((int)OpIdx1 == Src0Idx && !MO1->isReg() && in isLegalToSwap()
2809 !isInlineConstant(*MO1, OpInfo0)) in isLegalToSwap()
2818 if ((int)OpIdx0 != Src0Idx && MO1->isReg()) { in isLegalToSwap()
2821 return isLegalRegOperand(MI, OpIdx0, *MO1); in isLegalToSwap()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp3214 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr() local
3216 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
3219 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1922 MachineOperand &MO1 = MI.getOperand(1); in narrowScalar() local
1923 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); in narrowScalar()
1924 MO1.setReg(TruncMIB.getReg(0)); in narrowScalar()