1 /*- 2 * Copyright (c) 2016-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef __MLX5_PORT_H__ 27 #define __MLX5_PORT_H__ 28 29 #include <dev/mlx5/driver.h> 30 31 enum mlx5_beacon_duration { 32 MLX5_BEACON_DURATION_OFF = 0x0, 33 MLX5_BEACON_DURATION_INF = 0xffff, 34 }; 35 36 enum mlx5_module_id { 37 MLX5_MODULE_ID_SFP = 0x3, 38 MLX5_MODULE_ID_QSFP = 0xC, 39 MLX5_MODULE_ID_QSFP_PLUS = 0xD, 40 MLX5_MODULE_ID_QSFP28 = 0x11, 41 }; 42 43 enum mlx5_an_status { 44 MLX5_AN_UNAVAILABLE = 0, 45 MLX5_AN_COMPLETE = 1, 46 MLX5_AN_FAILED = 2, 47 MLX5_AN_LINK_UP = 3, 48 MLX5_AN_LINK_DOWN = 4, 49 }; 50 51 /* EEPROM I2C Addresses */ 52 #define MLX5_I2C_ADDR_LOW 0x50 53 #define MLX5_I2C_ADDR_HIGH 0x51 54 #define MLX5_EEPROM_PAGE_LENGTH 256 55 #define MLX5_EEPROM_MAX_BYTES 32 56 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 57 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 58 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 59 #define MLX5_EEPROM_LOW_PAGE 0x0 60 #define MLX5_EEPROM_HIGH_PAGE 0x3 61 #define MLX5_EEPROM_HIGH_PAGE_OFFSET 128 62 #define MLX5_EEPROM_INFO_BYTES 0x3 63 64 /* EEPROM Standards for plug in modules */ 65 #ifndef MLX5_ETH_MODULE_SFF_8472 66 #define MLX5_ETH_MODULE_SFF_8472 0x1 67 #define MLX5_ETH_MODULE_SFF_8472_LEN 128 68 #endif 69 70 #ifndef MLX5_ETH_MODULE_SFF_8636 71 #define MLX5_ETH_MODULE_SFF_8636 0x2 72 #define MLX5_ETH_MODULE_SFF_8636_LEN 256 73 #endif 74 75 #ifndef MLX5_ETH_MODULE_SFF_8436 76 #define MLX5_ETH_MODULE_SFF_8436 0x3 77 #define MLX5_ETH_MODULE_SFF_8436_LEN 256 78 #endif 79 80 enum mlx5e_link_speed { 81 MLX5E_1000BASE_CX_SGMII = 0, 82 MLX5E_1000BASE_KX = 1, 83 MLX5E_10GBASE_CX4 = 2, 84 MLX5E_10GBASE_KX4 = 3, 85 MLX5E_10GBASE_KR = 4, 86 MLX5E_20GBASE_KR2 = 5, 87 MLX5E_40GBASE_CR4 = 6, 88 MLX5E_40GBASE_KR4 = 7, 89 MLX5E_56GBASE_R4 = 8, 90 MLX5E_10GBASE_CR = 12, 91 MLX5E_10GBASE_SR = 13, 92 MLX5E_10GBASE_ER_LR = 14, 93 MLX5E_40GBASE_SR4 = 15, 94 MLX5E_40GBASE_LR4_ER4 = 16, 95 MLX5E_50GBASE_SR2 = 18, 96 MLX5E_50GBASE_KR4 = 19, 97 MLX5E_100GBASE_CR4 = 20, 98 MLX5E_100GBASE_SR4 = 21, 99 MLX5E_100GBASE_KR4 = 22, 100 MLX5E_100GBASE_LR4 = 23, 101 MLX5E_100BASE_TX = 24, 102 MLX5E_1000BASE_T = 25, 103 MLX5E_10GBASE_T = 26, 104 MLX5E_25GBASE_CR = 27, 105 MLX5E_25GBASE_KR = 28, 106 MLX5E_25GBASE_SR = 29, 107 MLX5E_50GBASE_CR2 = 30, 108 MLX5E_50GBASE_KR2 = 31, 109 MLX5E_LINK_SPEEDS_NUMBER = 32, 110 }; 111 112 enum mlx5e_ext_link_speed { 113 MLX5E_SGMII_100M = 0, 114 MLX5E_1000BASE_X_SGMII = 1, 115 MLX5E_5GBASE_R = 3, 116 MLX5E_10GBASE_XFI_XAUI_1 = 4, 117 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, 118 MLX5E_25GAUI_1_25GBASE_CR_KR = 6, 119 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, 120 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, 121 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, 122 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, 123 MLX5E_100GAUI_1_100GBASE_CR_KR = 11, 124 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, 125 MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, 126 MLX5E_400GAUI_8 = 15, 127 MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, 128 MLX5E_EXT_LINK_SPEEDS_NUMBER = 32, 129 }; 130 131 enum mlx5e_connector_type { 132 MLX5E_PORT_UNKNOWN = 0, 133 MLX5E_PORT_NONE = 1, 134 MLX5E_PORT_TP = 2, 135 MLX5E_PORT_AUI = 3, 136 MLX5E_PORT_BNC = 4, 137 MLX5E_PORT_MII = 5, 138 MLX5E_PORT_FIBRE = 6, 139 MLX5E_PORT_DA = 7, 140 MLX5E_PORT_OTHER = 8, 141 MLX5E_CONNECTOR_TYPE_NUMBER = 9, 142 }; 143 144 enum mlx5e_cable_type { 145 MLX5E_CABLE_TYPE_UNKNOWN = 0, 146 MLX5E_CABLE_TYPE_ACTIVE_CABLE = 1, 147 MLX5E_CABLE_TYPE_OPTICAL_MODULE = 2, 148 MLX5E_CABLE_TYPE_PASSIVE_COPPER = 3, 149 MLX5E_CABLE_TYPE_CABLE_UNPLUGGED = 4, 150 MLX5E_CABLE_TYPE_TWISTED_PAIR = 5, 151 MLX5E_CABLE_TYPE_NUMBER = 8, 152 }; 153 154 enum mlx5_qpts_trust_state { 155 MLX5_QPTS_TRUST_PCP = 1, 156 MLX5_QPTS_TRUST_DSCP = 2, 157 MLX5_QPTS_TRUST_BOTH = 3, 158 }; 159 struct mlx5e_port_eth_proto { 160 u32 cap; 161 u32 admin; 162 u32 oper; 163 }; 164 165 #ifndef SPEED_40000 166 #define SPEED_40000 40000 167 #endif 168 169 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode)) 170 171 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 172 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 173 174 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ 175 ((ext) ? MLX5_GET(reg, out, ext_##field) : \ 176 MLX5_GET(reg, out, field)) 177 178 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 179 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 180 int ptys_size, int proto_mask, u8 local_port); 181 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 182 u32 *proto_cap, int proto_mask); 183 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, 184 u8 *an_disable_cap, u8 *an_disable_status); 185 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable, 186 u32 eth_proto_admin, int proto_mask); 187 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 188 u32 *proto_admin, int proto_mask); 189 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev, 190 u32 *proto_oper, u8 local_port); 191 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 192 int proto_mask, bool ext); 193 int mlx5_set_port_status(struct mlx5_core_dev *dev, 194 enum mlx5_port_status status); 195 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 196 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 197 enum mlx5_port_status *status); 198 int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port, 199 u8 rx_pause, u8 tx_pause, 200 u8 pfc_en_rx, u8 pfc_en_tx); 201 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 202 u32 *rx_pause, u32 *tx_pause); 203 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx); 204 205 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 206 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 207 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 208 209 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 210 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 211 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 212 int device_addr, int size, int module_num, u32 *data, 213 int *size_read); 214 215 int mlx5_max_tc(struct mlx5_core_dev *mdev); 216 int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev, 217 u8 *max_bw_value, 218 u8 *max_bw_units); 219 int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev, 220 const u8 *max_bw_value, 221 const u8 *max_bw_units); 222 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 223 u8 prio, u8 *tc); 224 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index, 225 const u8 prio_tc); 226 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group); 227 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 228 u8 tc, u8 *tc_group); 229 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw); 230 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct); 231 232 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); 233 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); 234 235 #define MLX5_MAX_SUPPORTED_DSCP 64 236 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio); 237 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); 238 239 int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type); 240 int mlx5_query_pddr_cable_type(struct mlx5_core_dev *mdev, u8 local_port, u8 *cable_type); 241 242 u32 mlx5e_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper); 243 int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); 244 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, 245 struct mlx5e_port_eth_proto *eproto); 246 247 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out); 248 int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in); 249 int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer); 250 int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer); 251 252 #endif /* __MLX5_PORT_H__ */ 253