Home
last modified time | relevance | path

Searched refs:MLD (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DDebugInfo.cpp754 DILocation *getReplacementMDLocation(DILocation *MLD) { in getReplacementMDLocation() argument
755 auto *Scope = map(MLD->getScope()); in getReplacementMDLocation()
756 auto *InlinedAt = map(MLD->getInlinedAt()); in getReplacementMDLocation()
757 if (MLD->isDistinct()) in getReplacementMDLocation()
758 return DILocation::getDistinct(MLD->getContext(), MLD->getLine(), in getReplacementMDLocation()
759 MLD->getColumn(), Scope, InlinedAt); in getReplacementMDLocation()
760 return DILocation::get(MLD->getContext(), MLD->getLine(), MLD->getColumn(), in getReplacementMDLocation()
796 if (auto *MLD = dyn_cast<DILocation>(N)) in remap() local
797 return getReplacementMDLocation(MLD); in remap()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2311 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, in SplitVecRes_MLOAD() argument
2313 assert(MLD->isUnindexed() && "Indexed masked load during type legalization!"); in SplitVecRes_MLOAD()
2315 SDLoc dl(MLD); in SplitVecRes_MLOAD()
2316 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0)); in SplitVecRes_MLOAD()
2318 SDValue Ch = MLD->getChain(); in SplitVecRes_MLOAD()
2319 SDValue Ptr = MLD->getBasePtr(); in SplitVecRes_MLOAD()
2320 SDValue Offset = MLD->getOffset(); in SplitVecRes_MLOAD()
2322 SDValue Mask = MLD->getMask(); in SplitVecRes_MLOAD()
2323 SDValue PassThru = MLD->getPassThru(); in SplitVecRes_MLOAD()
2324 Align Alignment = MLD->getBaseAlign(); in SplitVecRes_MLOAD()
[all …]
H A DLegalizeTypes.h973 void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
H A DDAGCombiner.cpp12782 MaskedLoadSDNode *MLD = cast<MaskedLoadSDNode>(N); in visitMLOAD() local
12783 SDValue Mask = MLD->getMask(); in visitMLOAD()
12787 return CombineTo(N, MLD->getPassThru(), MLD->getChain()); in visitMLOAD()
12791 if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MLD->isUnindexed() && in visitMLOAD()
12792 !MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) { in visitMLOAD()
12794 N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(), in visitMLOAD()
12795 MLD->getPointerInfo(), MLD->getBaseAlign(), in visitMLOAD()
12796 MLD->getMemOperand()->getFlags(), MLD->getAAInfo(), MLD->getRanges()); in visitMLOAD()
H A DSelectionDAG.cpp886 const MaskedLoadSDNode *MLD = cast<MaskedLoadSDNode>(N); in AddNodeIDCustom() local
887 ID.AddInteger(MLD->getMemoryVT().getRawBits()); in AddNodeIDCustom()
888 ID.AddInteger(MLD->getRawSubclassData()); in AddNodeIDCustom()
889 ID.AddInteger(MLD->getPointerInfo().getAddrSpace()); in AddNodeIDCustom()
890 ID.AddInteger(MLD->getMemOperand()->getFlags()); in AddNodeIDCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp23043 MaskedLoadSDNode *MLD = cast<MaskedLoadSDNode>(N->getOperand(0)); in performUnpackCombine() local
23044 SDValue Mask = MLD->getMask(); in performUnpackCombine()
23047 if (MLD->isUnindexed() && MLD->getExtensionType() != ISD::SEXTLOAD && in performUnpackCombine()
23048 SDValue(MLD, 0).hasOneUse() && Mask->getOpcode() == AArch64ISD::PTRUE && in performUnpackCombine()
23049 (MLD->getPassThru()->isUndef() || in performUnpackCombine()
23050 isZerosVector(MLD->getPassThru().getNode()))) { in performUnpackCombine()
23063 VT, DL, MLD->getChain(), MLD->getBasePtr(), MLD->getOffset(), Mask, in performUnpackCombine()
23064 PassThru, MLD->getMemoryVT(), MLD->getMemOperand(), in performUnpackCombine()
23065 MLD->getAddressingMode(), ISD::ZEXTLOAD); in performUnpackCombine()
23067 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), NewLoad.getValue(1)); in performUnpackCombine()
/freebsd/share/doc/IPv6/
H A DIMPLEMENTATION1436 include, but may not be limited to, (1) MLD while no IPv6 address is assigned