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Searched refs:MIb (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ControlFlowFinalizer.cpp320 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
324 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
537 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
542 Pair.second.insert(MIb); in runOnMachineFunction()
562 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
566 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
567 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
576 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
580 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
581 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
[all …]
H A DSIInstrInfo.cpp3699 const MachineInstr &MIb) const { in checkInstOffsetsDoNotOverlap()
3706 !getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable, in checkInstOffsetsDoNotOverlap()
3713 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
3718 LocationSize Width1 = MIb.memoperands().front()->getSize(); in checkInstOffsetsDoNotOverlap()
3723 const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
3726 assert(MIb.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
3729 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
3733 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
3736 if (isLDSDMA(MIa) || isLDSDMA(MIb)) in areMemAccessesTriviallyDisjoint()
3745 if (isDS(MIb)) in areMemAccessesTriviallyDisjoint()
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H A DSIInstrInfo.h177 const MachineInstr &MIb) const;
390 const MachineInstr &MIb) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp574 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
582 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
587 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
596 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
610 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
622 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
628 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
629 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
631 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
632 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
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H A DHexagonMCCompound.cpp336 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
338 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
346 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
H A DHexagonMCInstrInfo.h240 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
277 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
H A DLanaiInstrInfo.h39 const MachineInstr &MIb) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h294 const MachineInstr &MIb) const override;
367 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
H A DHexagonInstrInfo.cpp1987 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
1988 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1989 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1994 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
2007 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB)) in areMemAccessesTriviallyDisjoint()
2009 const MachineOperand &BaseB = MIb.getOperand(BasePosB); in areMemAccessesTriviallyDisjoint()
2018 unsigned SizeB = getMemAccessSize(MIb); in areMemAccessesTriviallyDisjoint()
2022 const MachineOperand &OffB = MIb.getOperand(OffsetPosB); in areMemAccessesTriviallyDisjoint()
2024 !MIb.getOperand(OffsetPosB).isImm()) in areMemAccessesTriviallyDisjoint()
2027 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm(); in areMemAccessesTriviallyDisjoint()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h385 const MachineInstr &MIb) const override;
H A DSystemZInstrInfo.cpp2262 const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
2264 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) in areMemAccessesTriviallyDisjoint()
2272 MachineMemOperand *MMOb = *MIb.memoperands_begin(); in areMemAccessesTriviallyDisjoint()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h187 const MachineInstr &MIb) const override;
H A DRISCVInstrInfo.cpp2747 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
2749 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
2751 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
2752 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
2765 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1965 const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1968 assert(MIb.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h197 const MachineInstr &MIb) const override;
H A DAArch64LoadStoreOptimizer.cpp1282 for (MachineInstr *MIb : MemInsns) { in mayAlias()
1283 if (MIa.mayAlias(AA, *MIb, /*UseTBAA*/ false)) { in mayAlias()
1284 LLVM_DEBUG(dbgs() << "Aliasing with: "; MIb->dump()); in mayAlias()
H A DAArch64InstrInfo.cpp1102 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
1110 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
1112 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1113 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1125 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, OffsetBIsScalable, in areMemAccessesTriviallyDisjoint()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h586 const MachineInstr &MIb) const override;
H A DPPCInstrInfo.cpp5551 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
5553 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
5555 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
5556 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
5569 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
/freebsd/sys/cddl/dev/dtrace/x86/
H A Ddis_tables.c154 MIb, /* for 386 logicals */ enumerator
623 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
4897 case MIb: in dtrace_disx86()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp1460 MachineInstr *MIb = &*MBBb; in reportIPToStateForBlocks() local
1461 if (MIb->isTerminator()) in reportIPToStateForBlocks()