| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 335 static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair() argument
337 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); in isOrderedCompoundPair()
341 unsigned Opca = MIa.getOpcode(); in isOrderedCompoundPair()
346 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
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| H A D | HexagonMCDuplexInfo.cpp | 573 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair() argument
586 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), in isOrderedDuplexPair()
595 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); in isOrderedDuplexPair()
617 if (subInstWouldBeExtended(MIa)) in isOrderedDuplexPair()
651 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
652 unsigned MIaG = getDuplexCandidateGroup(MIa), in isDuplexPair()
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| H A D | HexagonMCInstrInfo.h | 240 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
276 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
90 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
106 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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| H A D | LanaiInstrInfo.h | 38 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 293 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
367 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
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| H A D | HexagonInstrInfo.cpp | 1987 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1988 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1989 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1994 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1999 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA)) in areMemAccessesTriviallyDisjoint()
2001 const MachineOperand &BaseA = MIa.getOperand(BasePosA); in areMemAccessesTriviallyDisjoint()
2017 unsigned SizeA = getMemAccessSize(MIa); in areMemAccessesTriviallyDisjoint()
2021 const MachineOperand &OffA = MIa.getOperand(OffsetPosA); in areMemAccessesTriviallyDisjoint()
2023 if (!MIa.getOperand(OffsetPosA).isImm() || in areMemAccessesTriviallyDisjoint()
2026 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm(); in areMemAccessesTriviallyDisjoint()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 384 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | SystemZInstrInfo.cpp | 2261 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
2264 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) in areMemAccessesTriviallyDisjoint()
2271 MachineMemOperand *MMOa = *MIa.memoperands_begin(); in areMemAccessesTriviallyDisjoint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 186 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | RISCVInstrInfo.cpp | 2747 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
2748 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
2751 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
2752 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
2764 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
2740 areMemAccessesTriviallyDisjoint(const MachineInstr & MIa,const MachineInstr & MIb) const areMemAccessesTriviallyDisjoint() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 3698 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa, in checkInstOffsetsDoNotOverlap() argument
3704 if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable, in checkInstOffsetsDoNotOverlap()
3713 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
3717 LocationSize Width0 = MIa.memoperands().front()->getSize(); in checkInstOffsetsDoNotOverlap()
3722 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
3724 assert(MIa.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
3729 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
3733 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
3736 if (isLDSDMA(MIa) || isLDSDMA(MIb)) in areMemAccessesTriviallyDisjoint()
3744 if (isDS(MIa)) { in areMemAccessesTriviallyDisjoint()
[all …]
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| H A D | SIInstrInfo.h | 176 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
389 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1964 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
1966 assert(MIa.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 196 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | AArch64LoadStoreOptimizer.cpp | 1279 static bool mayAlias(MachineInstr &MIa, in mayAlias() argument
1283 if (MIa.mayAlias(AA, *MIb, /*UseTBAA*/ false)) { in mayAlias()
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| H A D | AArch64InstrInfo.cpp | 1102 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1109 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
1112 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1113 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1123 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, OffsetAIsScalable, in areMemAccessesTriviallyDisjoint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 585 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | PPCInstrInfo.cpp | 5551 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
5552 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
5555 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
5556 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
5568 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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