Home
last modified time | relevance | path

Searched refs:MIPS (Results 1 – 25 of 113) sorted by relevance

12345

/freebsd/contrib/file/magic/Magdir/
H A Dmips4 # mips: file(1) magic for MIPS ECOFF and Ucode, as used in SGI IRIX
16 # MIPS 1
38 # MIPS 2 additions
41 >16 beshort 56 MIPSEB MIPS-II ECOFF executable
45 >16 beshort 56 MIPSEL-BE MIPS-II ECOFF executable
51 >16 leshort 56 MIPSEB-LE MIPS-II ECOFF executable
55 >16 leshort 56 MIPSEL MIPS-II ECOFF executable
60 # MIPS 3 additions
63 >16 beshort 56 MIPSEB MIPS-III ECOFF executable
67 >16 beshort 56 MIPSEL-BE MIPS-III ECOFF executable
[all …]
H A Dplan912 0 belong 0x00000407 Plan 9 executable, MIPS R3000
14 0 belong 0x00000517 Plan 9 executable, MIPS R4000 BE
18 0 belong 0x00000797 Plan 9 executable, MIPS R4000 LE
21 0 belong 0x3A11013C Plan 9 object file, MIPS R3000
H A Dolf9 # MIPS R3000 may also be for MIPS R2000.
51 >>18 leshort 8 MIPS R3000_BE - invalid byte order,
53 >>18 leshort 10 MIPS R3000_LE,
82 >>18 beshort 8 MIPS R3000_BE,
84 >>18 beshort 10 MIPS R3000_LE - invalid byte order,
H A Delf21 >0 lelong&0xf0000000 0x00000000 MIPS-I
22 >0 lelong&0xf0000000 0x10000000 MIPS-II
23 >0 lelong&0xf0000000 0x20000000 MIPS-III
24 >0 lelong&0xf0000000 0x30000000 MIPS-IV
25 >0 lelong&0xf0000000 0x40000000 MIPS-V
94 # The official e_machine number for MIPS is now #8, regardless of endianness.
97 >18 leshort 8 MIPS,
100 >18 leshort 10 MIPS,
111 >18 leshort 10 MIPS (deprecated),
158 >18 leshort 51 Stanford MIPS-X,
H A Dcoff20 >0 uleshort 0x0160 MIPS R3000 (big-endian)
21 >0 uleshort 0x0162 MIPS R3000
22 >0 uleshort 0x0166 MIPS R4000
23 >0 uleshort 0x0168 MIPS R10000
24 >0 uleshort 0x0169 MIPS WCE v2
45 >0 uleshort 0x0366 MIPS with FPU
H A Ddigital72 # Locale data tables (MIPS and Alpha).
76 >6 short 0x24 for MIPS
H A Dparrot17 >32 byte 3 MIPS 16 byte long double floats,
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DMips.cpp22 template <class ELFT> class MIPS final : public TargetInfo { class
24 MIPS(Ctx &);
43 template <class ELFT> MIPS<ELFT>::MIPS(Ctx &ctx) : TargetInfo(ctx) { in MIPS() function in MIPS
70 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { in calcEFlags()
75 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s, in getRelExpr()
198 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const { in getDynRel()
205 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const { in writeGotPlt()
257 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const { in writePltHeader()
320 void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym, in writePlt()
359 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file, in needsThunk()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips.td89 "Subset of MIPS-III that is also in MIPS32 "
92 "Subset of MIPS-III that is also in MIPS32r2 "
95 "MIPS III ISA Support [highly experimental]",
100 "Subset of MIPS-IV that is also in MIPS32 "
103 "Subset of MIPS-IV that is also in MIPS32r2 "
106 "Mips4", "MIPS IV ISA Support",
110 "Subset of MIPS-V that is also in MIPS32r2 "
113 "MIPS V ISA Support [highly experimental]",
246 "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
250 "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
H A DMipsMTInstrInfo.td9 // This file describes the MIPS MT ASE as defined by MD00378 1.12.
17 // MIPS MT Instruction Encodings
41 // MIPS MT Instruction Descriptions
93 // MIPS MT Instruction Definitions
115 // MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.
176 // MIPS MT Instruction Definitions
/freebsd/sys/contrib/device-tree/Bindings/mips/
H A Dcpu_irq.txt1 MIPS CPU interrupt controller
3 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
H A Dmscc.txt1 * Microsemi MIPS CPUs
3 Boards with a SoC of the Microsemi MIPS family shall have the following
H A Dni.txt1 National Instruments MIPS platforms
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DDwarf.def227 HANDLE_DW_TAG(0x4081, MIPS_loop, 0, MIPS, DW_KIND_NONE)
424 HANDLE_DW_AT(0x2001, MIPS_fde, 0, MIPS)
425 HANDLE_DW_AT(0x2002, MIPS_loop_begin, 0, MIPS)
426 HANDLE_DW_AT(0x2003, MIPS_tail_loop_begin, 0, MIPS)
427 HANDLE_DW_AT(0x2004, MIPS_epilog_begin, 0, MIPS)
428 HANDLE_DW_AT(0x2005, MIPS_loop_unroll_factor, 0, MIPS)
429 HANDLE_DW_AT(0x2006, MIPS_software_pipeline_depth, 0, MIPS)
430 HANDLE_DW_AT(0x2007, MIPS_linkage_name, 0, MIPS)
433 HANDLE_DW_AT(0x2008, MIPS_stride, 0, MIPS)
434 HANDLE_DW_AT(0x2009, MIPS_abstract_name, 0, MIPS)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mips/img/
H A Dxilfpga.txt7 As we are dealing with a MIPS core instantiated on an FPGA, specifications
43 - clocks: phandle to ext clock for fixed-clock received by MIPS core.
/freebsd/tools/build/options/
H A DWITH_LLVM_TARGET_MIPS
H A DWITHOUT_LLVM_TARGET_MIPS
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXMips.td9 // This file describes the vendor extensions defined by MIPS.
39 // MIPS custom instruction formats
129 // MIPS extensions
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmips-gic.txt1 MIPS Global Interrupt Controller (GIC)
3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
/freebsd/sys/contrib/device-tree/Bindings/mips/brcm/
H A Dbrcm,bmips.txt1 * Broadcom MIPS (BMIPS) CPUs
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Dmti,mips-cpc.txt1 Binding for MIPS Cluster Power Controller (CPC).
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Docelot-reset.txt6 The reset registers are both present in the MSCC vcoreiii MIPS and
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dbrcm,bcm63xx-clocks.txt1 Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-mt7621.txt1 Binding for MTK SPI controller (MT7621 MIPS)
/freebsd/crypto/openssl/util/
H A Dshlib_wrap.sh58 *ELF\ 32*MIPS*)

12345