Searched refs:MIMG (Results 1 – 14 of 14) sorted by relevance
1 //===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===//9 // MIMG-specific encoding families to distinguish between semantically99 def MIMG {109 bit HAS_GFX12 = !ne(gfx12, MIMG.NOP);110 bit HAS_GFX11 = !ne(gfx11, MIMG.NOP);111 bit HAS_GFX10M = !ne(gfx10m, MIMG.NOP);112 bit HAS_VI = !ne(vi, MIMG.NOP);113 bit HAS_SI = !ne(si, MIMG.NOP);201 let MIMG = 1;213 class MIMG <dag outs, string dns = "">[all …]
82 MIMG, enumerator183 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()474 return MIMG; in getInstClass()833 if (InstClass == MIMG) { in setMI()849 } else if (InstClass != MIMG) { in setMI()960 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()1036 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()1216 if (CI.InstClass == MIMG) { in checkAndPrepareMerge()1875 case MIMG: in getNewOpcode()1885 assert((CI.InstClass != MIMG || in getSubRegIdxs()[all …]
67 SIInstrFlags::FLAT | SIInstrFlags::MIMG |
42 field bit MIMG = 0;186 let TSFlags{20} = MIMG;
37 SIInstrFlags::FLAT | SIInstrFlags::MIMG | in instructionWaitsForVALU()
84 MIMG = 1 << 20, enumerator
600 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()604 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
289 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"295 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
5802 (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) { in adjustAllocatableRegClass()
273 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()307 MCID.TSFlags & SIInstrFlags::MIMG || MCID.TSFlags & SIInstrFlags::FLAT; in isVMEM()
409 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
842 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) { in getInstruction()1179 AMDGPU::OpName RsrcOpName = (TSFlags & SIInstrFlags::MIMG) in convertMIMGInst()
4116 SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;4179 AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) in validateMIMGAddrSize()5101 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateAGPRLdSt()5301 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateCoherencyBits()5317 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
839 bit DA = 0; // DA bit in MIMG encoding