Searched refs:MIMG (Results 1 – 14 of 14) sorted by relevance
1 //===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===//9 // MIMG-specific encoding families to distinguish between semantically97 def MIMG {107 bit HAS_GFX12 = !ne(gfx12, MIMG.NOP);108 bit HAS_GFX11 = !ne(gfx11, MIMG.NOP);109 bit HAS_GFX10M = !ne(gfx10m, MIMG.NOP);110 bit HAS_VI = !ne(vi, MIMG.NOP);111 bit HAS_SI = !ne(si, MIMG.NOP);199 let MIMG = 1;211 class MIMG <dag outs, string dns = "">[all …]
81 MIMG, enumerator182 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()462 return MIMG; in getInstClass()797 if (InstClass == MIMG) { in setMI()813 } else if (InstClass != MIMG) { in setMI()924 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()1000 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()1180 if (CI.InstClass == MIMG) { in checkAndPrepareMerge()1814 case MIMG: in getNewOpcode()1824 assert((CI.InstClass != MIMG || in getSubRegIdxs()[all …]
61 SIInstrFlags::FLAT | SIInstrFlags::MIMG;
42 field bit MIMG = 0;182 let TSFlags{20} = MIMG;
46 SIInstrFlags::FLAT | SIInstrFlags::MIMG | in instructionWaitsForVALU()
83 MIMG = 1 << 20, enumerator
581 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()585 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
253 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"259 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
5555 (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) { in adjustAllocatableRegClass()
272 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()306 MCID.TSFlags & SIInstrFlags::MIMG; in isVMEM()
397 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
690 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) { in getInstruction()955 int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc in convertMIMGInst()
3856 SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;3919 int RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc in validateMIMGAddrSize()4735 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateAGPRLdSt()4931 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateCoherencyBits()4947 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
616 bit DA = 0; // DA bit in MIMG encoding