| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry)) in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1); in ReduceXWtoXWP()
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward); in ReduceXWtoXWP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SMEPeepholeOpt.cpp | 58 const MachineInstr *MI2) { in isMatchingStartStopPair() argument
61 if (MI1->getOperand(0).getImm() != MI2->getOperand(0).getImm()) in isMatchingStartStopPair()
65 if (MI1->getOperand(1).getImm() == MI2->getOperand(1).getImm()) in isMatchingStartStopPair()
68 bool IsConditional = isConditionalStartStop(MI2); in isMatchingStartStopPair()
76 if (MI1->getOperand(2).getImm() != MI2->getOperand(2).getImm()) in isMatchingStartStopPair()
80 if (MI1->getOperand(4).getRegMask() != MI2->getOperand(4).getRegMask()) in isMatchingStartStopPair()
93 if (MI1->getOperand(3).isReg() && MI2->getOperand(3).isReg()) { in isMatchingStartStopPair()
95 Register Reg2 = MI2->getOperand(3).getReg(); in isMatchingStartStopPair()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 490 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
525 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
526 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
529 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
530 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
535 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
536 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
547 MI2->getParent()); in hoistAndMergeSGPRInits()
554 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
559 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
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| H A D | SIInstrInfo.cpp | 530 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
538 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
542 auto *MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 273 const MachineInstr &MI2, in alias() argument
275 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
279 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
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| H A D | TargetInstrInfo.cpp | 919 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
923 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
926 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
939 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
945 areOpcodesEqualOrInverse(Opcode, MI2->getOpcode()); in hasReassociableSibling()
947 std::swap(MI1, MI2); in hasReassociableSibling()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelperVectorOps.cpp | 149 const MachineInstr &MI, const MachineInstr &MI2, in matchExtractVectorElementWithBuildVector() argument
152 const GBuildVector *Build = cast<GBuildVector>(&MI2); in matchExtractVectorElementWithBuildVector()
256 const MachineInstr &MI, const MachineInstr &MI2, in matchExtractVectorElementWithShuffleVector() argument
259 const GShuffleVector *Shuffle = cast<GShuffleVector>(&MI2); in matchExtractVectorElementWithShuffleVector()
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| H A D | LoadStoreOpt.cpp | 102 const MachineInstr &MI2, in aliasIsKnownForLoadStore() argument
106 auto *LdSt2 = dyn_cast<GLoadStore>(&MI2); in aliasIsKnownForLoadStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 272 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
273 if (!QII->isHVXVec(MI2)) in apply()
275 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
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| H A D | HexagonVLIWPacketizer.h | 144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| H A D | HexagonInstrInfo.h | 409 const MachineInstr &MI2) const;
421 const MachineInstr &MI2) const;
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| H A D | HexagonVLIWPacketizer.cpp | 959 MachineInstr &MI2) { in arePredicatesComplements() argument
963 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
1016 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
1020 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1021 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
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| H A D | HexagonInstrInfo.cpp | 2691 const MachineInstr &MI2) const { in isToBeScheduledASAP()
2695 int N = MI2.getNumOperands(); in isToBeScheduledASAP()
2697 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2700 if (mayBeNewStore(MI2)) in isToBeScheduledASAP()
2701 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2702 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2703 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3068 const MachineInstr &MI2) const { in addLatencyToSchedule()
3069 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3070 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| H A D | HexagonPatterns.td | 881 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
883 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
905 class T4<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3, InstHexagon MI4>
907 (MI1 (MI2 (MI3 $Rs, $Rt), (MI4 $Rs, $Rt)))>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 277 const MachineInstr &MI2, unsigned N2) const;
399 const MachineInstr &MI2, in getAddrDispShift() argument
402 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
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| H A D | X86ISelLowering.h | 1861 MachineInstr &MI2,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 314 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
318 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 215 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.h | 65 const MachineInstr &MI2, bool &IsAlias,
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| H A D | CombinerHelper.h | 902 const MachineInstr &MI2,
914 const MachineInstr &MI2,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 333 const MachineInstr &MI2) const;
349 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
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| H A D | RISCVInstrInfo.cpp | 2227 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(3).getReg()); in hasReassociableVectorSibling() local
2232 areRVVInstsReassociable(Inst, *MI2); in hasReassociableVectorSibling()
2234 std::swap(MI1, MI2); in hasReassociableVectorSibling()
2256 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
2260 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
2263 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
3203 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
3211 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
3215 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
4658 bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) { in hasEqualFRM() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1653 auto MI2 = in expandLSLW4Rd() local
1659 MI2->getOperand(3).setIsDead(); in expandLSLW4Rd()
1851 auto MI2 = in expandLSRW4Rd() local
1857 MI2->getOperand(3).setIsDead(); in expandLSRW4Rd()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | AsmPrinter.cpp | 1880 auto MI2 = std::next(MI.getIterator()); in emitFunctionBody() local
1881 if (IsEHa && MI2 != MBB.end() && in emitFunctionBody()
1882 (MI2->mayLoadOrStore() || MI2->mayRaiseFPException())) in emitFunctionBody()
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