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Searched refs:MI2 (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry)) in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1); in ReduceXWtoXWP()
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward); in ReduceXWtoXWP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp461 MachineInstr *MI2 = nullptr; eliminateTruncSeq() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp476 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
511 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
512 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
515 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
516 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
521 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
522 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
533 MI2->getParent()); in hoistAndMergeSGPRInits()
540 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
545 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
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H A DSIInstrInfo.cpp520 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
528 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
532 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp273 const MachineInstr &MI2, in alias() argument
275 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
279 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
H A DTargetInstrInfo.cpp842 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
846 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
849 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
862 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
868 areOpcodesEqualOrInverse(Opcode, MI2->getOpcode()); in hasReassociableSibling()
870 std::swap(MI1, MI2); in hasReassociableSibling()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp273 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
274 if (!QII->isHVXVec(MI2)) in apply()
276 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
H A DHexagonVLIWPacketizer.h144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
H A DHexagonInstrInfo.h408 const MachineInstr &MI2) const;
420 const MachineInstr &MI2) const;
H A DHexagonVLIWPacketizer.cpp968 MachineInstr &MI2) { in arePredicatesComplements() argument
972 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
1025 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
1029 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1030 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
H A DHexagonInstrInfo.cpp2688 const MachineInstr &MI2) const { in isToBeScheduledASAP()
2692 int N = MI2.getNumOperands(); in isToBeScheduledASAP()
2694 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2697 if (mayBeNewStore(MI2)) in isToBeScheduledASAP()
2698 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2699 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2700 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3064 const MachineInstr &MI2) const { in addLatencyToSchedule()
3065 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3066 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
H A DHexagonPatterns.td876 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
878 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp277 const MachineInstr &MI2, unsigned N2) const;
399 const MachineInstr &MI2, in getAddrDispShift() argument
402 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
H A DX86ISelLowering.h1769 MachineInstr &MI2,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h61 /// \p MI2 \returns true if either alias/no-alias is known. Sets \p IsAlias
63 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp314 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
318 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h313 const MachineInstr &MI2) const;
339 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
H A DRISCVInstrInfo.cpp1823 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(3).getReg()); in hasReassociableVectorSibling() local
1828 areRVVInstsReassociable(Inst, *MI2); in hasReassociableVectorSibling()
1830 std::swap(MI1, MI2); in hasReassociableVectorSibling()
1852 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
1856 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
1859 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
2659 const MachineInstr &MI2, in memOpsHaveSameBasePtr()
2667 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
2671 auto MO2 = *MI2 in memOpsHaveSameBasePtr()
2652 memOpsHaveSameBasePtr(const MachineInstr & MI1,ArrayRef<const MachineOperand * > BaseOps1,const MachineInstr & MI2,ArrayRef<const MachineOperand * > BaseOps2) memOpsHaveSameBasePtr() argument
3866 hasEqualFRM(const MachineInstr & MI1,const MachineInstr & MI2) hasEqualFRM() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDFAPacketizer.h215 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp105 const MachineInstr &MI2, in aliasIsKnownForLoadStore() argument
109 auto *LdSt2 = dyn_cast<GLoadStore>(&MI2); in aliasIsKnownForLoadStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp1655 auto MI2 = in expandLSLW4Rd() local
1661 MI2->getOperand(3).setIsDead(); in expandLSLW4Rd()
1853 auto MI2 = in expandLSRW4Rd() local
1859 MI2->getOperand(3).setIsDead(); in expandLSRW4Rd()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp1767 auto MI2 = std::next(MI.getIterator()); in emitFunctionBody() local
1768 if (IsEHa && MI2 != MBB.end() && in emitFunctionBody()
1769 (MI2->mayLoadOrStore() || MI2->mayRaiseFPException())) in emitFunctionBody()