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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
H A Dstmpe.txt28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
297 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
H A Dintegratorap.dts31 * that the maximum frequency for this clock is 200 MHz
33 * is actually just hanging the system above 71 MHz.
59 /* 24 MHz chrystal on the Integrator/AP development board */
66 /* The UART clock is 14.74 MHz divided by an ICS525 */
75 /* 24 MHz chrystal on the core module */
92 /* Auxilary oscillator on the core module, 32.369MHz at boot */
123 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-mickey.dts86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
206 /* When really hot, don't let GPU go _above_ 300 MHz */
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dtoshiba,tc358767.txt8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
H A Dti,sn65dsi86.txt29 clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Drockchip,dwc3.txt8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
11 operation and >= 30MHz for HS operation
/freebsd/sys/contrib/device-tree/Bindings/mips/cavium/
H A Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
H A Dgamecube.dts34 clock-frequency = <486000000>; /* 486MHz */
35 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
36 timebase-frequency = <40500000>; /* 162MHz / 4 */
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dstmpe.txt53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
78 /* 3.25 MHz ADC clock speed */
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroid-core.dtsi45 /* derived from 532MHz MPLL */
71 /* derived from 666MHz CPLL */
89 /* derived from 666MHz CPLL */
101 /* derived from 600MHz DPLL */
116 /* derived from 666MHz CPLL */
137 /* derived from 532MHz MPLL */
155 /* derived from 666MHz CPLL */
164 /* derived from 666MHz CPLL */
185 /* derived from 532MHz MPLL */
203 /* derived from 600MHz DPLL */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dufshcd-pltfrm.txt45 specification allows host to provide one of the 4 frequencies (19.2 MHz,
46 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
48 Defaults to 26 MHz(as per specification) if not specified by host.
/freebsd/sys/contrib/device-tree/Bindings/media/spi/
H A Dsony-cxd2880.txt6 - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
17 spi-max-frequency = <55000000>; /* 55MHz */
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
/freebsd/contrib/wpa/wpa_supplicant/
H A DREADME-NAN-USD29 …ice_name=<name> [ttl=<time-to-live-in-sec>] [freq=<in MHz>] [freq_list=<comma separate list of MHz…
34 If freq is not included, the default frequency 2437 MHz (channel 6 on
59 NAN_SUBSCRIBE service_name=<name> [active=1] [ttl=<time-to-live-in-sec>] [freq=<in MHz>] [srv_proto…
64 If freq is not included, the default frequency 2437 MHz (channel 6 on
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam5729-beagleboneai.dts422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
555 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
556 /* HS: High speed up to 50 MHz (3.3 V signaling). */
557 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
558 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
559 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
560 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
561 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dbrcm,bcm63xx-audio.txt13 - "i2sosc" (fixed 200MHz clock) Required.
17 (2) : The fixed 200MHz clock is from internal chip and always on
/freebsd/sys/contrib/device-tree/src/mips/cavium-octeon/
H A Docteon_3xxx.dts362 /* 12MHz, 24MHz and 48MHz allowed */
382 /* 12MHz, 24MHz and 48MHz allowed */
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
196 cpus 0,1@1GHz, cpus 2,3@500MHz):
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
196 cpus 0,1@1GHz, cpus 2,3@500MHz):

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