| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 92 ADD_VVP_OP(VVP_GATHER, MGATHER) HANDLE_VP_TO_VVP(VP_GATHER, VVP_GATHER)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1413 MGATHER, enumerator
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| H A D | SelectionDAGNodes.h | 1519 case ISD::MGATHER:
1563 case ISD::MGATHER:
3032 return N->getOpcode() == ISD::MGATHER || N->getOpcode() == ISD::MSCATTER ||
3046 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
3058 return N->getOpcode() == ISD::MGATHER;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 973 MGATHER, enumerator
1951 return N->getOpcode() == X86ISD::MGATHER || in classof()
1961 return N->getOpcode() == X86ISD::MGATHER; in classof()
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| H A D | X86ISelLowering.cpp | 1691 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom); in X86TargetLowering()
1692 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom); in X86TargetLowering()
1696 setOperationAction(ISD::MGATHER, VT, Custom); in X86TargetLowering()
2059 setOperationAction(ISD::MGATHER, VT, Custom); in X86TargetLowering()
2691 ISD::MGATHER, in X86TargetLowering()
27410 DAG.getMemIntrinsicNode(X86ISD::MGATHER, dl, VTs, Ops, in getAVX2GatherNode()
27448 DAG.getMemIntrinsicNode(X86ISD::MGATHER, dl, VTs, Ops, in getGatherNode()
33379 X86ISD::MGATHER, dl, DAG.getVTList(VT, MVT::Other), Ops, N->getMemoryVT(), in LowerMGATHER()
33724 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG); in LowerOperation()
34830 case ISD::MGATHER: { in ReplaceNodeResults()
[all …]
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| H A D | X86ISelDAGToDAG.cpp | 6490 case X86ISD::MGATHER: { in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 455 case ISD::MGATHER: return "masked_gather"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 1161 case ISD::MGATHER: in SplitVectorResult()
3441 case ISD::MGATHER: in SplitVectorOperand()
4721 case ISD::MGATHER: in WidenVectorResult()
6828 case ISD::MGATHER: Res = WidenVecOp_MGATHER(N, OpNo); break; in WidenVectorOperand()
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| H A D | LegalizeVectorOps.cpp | 474 case ISD::MGATHER: in LegalizeOp()
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| H A D | SelectionDAG.cpp | 901 case ISD::MGATHER: { in AddNodeIDCustom()
3957 case ISD::MGATHER: in computeKnownBits()
3960 (Opcode == ISD::MGATHER) in computeKnownBits()
10278 AddNodeIDNode(ID, ISD::MGATHER, VTs, Ops); in getMaskedGather()
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| H A D | LegalizeIntegerTypes.cpp | 91 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N)); in PromoteIntegerResult()
2004 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N), in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 2025 case ISD::MGATHER: return visitMGATHER(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 920 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1098 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1176 ISD::MGATHER, ISD::MSCATTER, ISD::VP_LOAD, in RISCVTargetLowering()
1345 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
1436 ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1649 {ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER, in RISCVTargetLowering()
8212 case ISD::MGATHER: in LowerOperation()
20106 case ISD::MGATHER: { in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 809 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1160 {ISD::MGATHER, ISD::MSCATTER, ISD::EXPERIMENTAL_VECTOR_HISTOGRAM}); in AArch64TargetLowering()
1923 setOperationAction(ISD::MGATHER, VT, Custom); in AArch64TargetLowering()
2315 setOperationAction(ISD::MGATHER, VT, PreferSVE ? Default : Expand); in addTypeForFixedLengthSVE()
7414 case ISD::MGATHER: in LowerOperation()
26814 case ISD::MGATHER: in PerformDAGCombine()
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