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Searched refs:MFMA (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUIGroupLP.cpp70 MFMA = 1u << 3, enumerator
78 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
880 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1721 SchedGroupMask::MFMA, MFMARatio, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1811 SchedGroupMask::MFMA, MFMAEnablement * 2, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1852 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2161 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2182 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2192 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2218 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
[all …]
H A DGCNHazardRecognizer.cpp2631 const MachineInstr *MFMA = nullptr; in checkMAIVALUHazards() local
2633 auto IsMFMAWriteFn = [&Reg, &MFMA, this](const MachineInstr &MI) { in checkMAIVALUHazards()
2637 MFMA = &MI; in checkMAIVALUHazards()
2718 MFMA = nullptr; in checkMAIVALUHazards()
2721 if (!MFMA) in checkMAIVALUHazards()
2724 unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA); in checkMAIVALUHazards()
2728 if (SIInstrInfo::isDGEMM(MFMA->getOpcode())) { in checkMAIVALUHazards()
2748 TII.isXDL(*MFMA) in checkMAIVALUHazards()
2814 MFMA = nullptr; in checkMAIVALUHazards()
2817 if (MFMA) { in checkMAIVALUHazards()
[all …]
H A DSIInstrFormats.td131 // This bit indicates that this is one of MFMA instructions.
H A DSISchedule.td129 def HWXDL : ProcResource<1> { // MFMA CU
H A DAMDGPU.td226 "MFMA cannot use inline literal as SrcC"
H A DVOP3PInstructions.td811 // Does this MFMA use "AGPR" or "VGPR" for srcC/vdst
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def371 // MFMA builtins.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td319 // MASK = 0x0000 0008: MFMA/WMMA instructions may be scheduled across SCHED_BARRIER.
3340 // Note: in gfx942 BLGP argument is replaced by NEG bitfield in the DGEMM MFMA.