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Searched refs:MERGE_VALUES (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h256 MERGE_VALUES, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1910 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1911 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp197 case ISD::MERGE_VALUES: return "merge_values"; in getOperationName()
H A DSelectionDAGBuilder.cpp957 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs()
3562 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, in visitLandingPad()
3874 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitSelect()
4307 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInsertValue()
4342 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitExtractValue()
4695 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, in visitLoad()
10449 if (Val.getOpcode() == ISD::MERGE_VALUES) { in visitInlineAsm()
10465 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInlineAsm()
11338 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, in LowerCallTo()
12662 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitFreeze()
[all …]
H A DLegalizeVectorOps.cpp314 case ISD::MERGE_VALUES: in LegalizeOp()
929 case ISD::MERGE_VALUES: in Expand()
H A DInstrEmitter.cpp1250 case ISD::MERGE_VALUES: in EmitSpecialNode()
H A DSelectionDAG.cpp3416 case ISD::MERGE_VALUES: in computeKnownBits()
4752 case ISD::MERGE_VALUES: in ComputeNumSignBits()
6363 case ISD::MERGE_VALUES: in getNode()
9299 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops); in getMergeValues()
10738 return getNode(ISD::MERGE_VALUES, DL, VTList, {N1, ZeroOverFlow}, Flags); in getNode()
10747 return getNode(ISD::MERGE_VALUES, DL, VTList, in getNode()
10754 return getNode(ISD::MERGE_VALUES, DL, VTList, in getNode()
10801 return getNode(ISD::MERGE_VALUES, DL, VTList, {Lo, Hi}, Flags); in getNode()
10817 return getNode(ISD::MERGE_VALUES, DL, VTList, {Result0, Result1}, Flags); in getNode()
H A DScheduleDAGRRList.cpp708 case ISD::MERGE_VALUES: in EmitNode()
H A DLegalizeFloatTypes.cpp66 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
1546 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandFloatResult()
H A DLegalizeVectorTypes.cpp56 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
1121 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in SplitVectorResult()
4674 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; in WidenVectorResult()
H A DLegalizeDAG.cpp1113 case ISD::MERGE_VALUES: in LegalizeOp()
3266 case ISD::MERGE_VALUES: in ExpandNode()
H A DLegalizeIntegerTypes.cpp58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
2950 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandIntegerResult()
H A DDAGCombiner.cpp1895 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); in visit()
16311 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
H A DTargetLowering.cpp11118 assert(Ret.getOpcode() == ISD::MERGE_VALUES && in forceExpandWideMUL()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4772 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Flag); in lowerXALUO()
4810 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4873 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Flag); in lowerUADDSUBO_CARRY()
4912 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerUADDSUBO_CARRY()
5330 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), in lowerINTRINSIC_WO_CHAIN()
8439 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), in combineFP_ROUND()
8503 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), in combineFP_EXTEND()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp3429 assert(S->getOpcode() == ISD::MERGE_VALUES); in LowerHvxOperationWrapper()
3488 assert(Load->getOpcode() == ISD::MERGE_VALUES); in ReplaceHvxNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp743 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
H A DSIISelLowering.cpp6770 if (Res.getOpcode() == ISD::MERGE_VALUES) { in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1650 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Overflow); in LowerXALUO()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24788 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); in LowerXALUO()
27688 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, in LowerINTRINSIC_W_CHAIN()
27701 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, in LowerINTRINSIC_W_CHAIN()
27771 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
27792 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
27828 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
27869 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
27882 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
27963 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Res, Chain); in LowerINTRINSIC_W_CHAIN()
27987 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Res, Chain); in LowerINTRINSIC_W_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5078 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerSignedALUO()
5139 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerUnsignedALUO()
9977 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry); in LowerUADDSUBO_CARRY()
10050 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, in LowerFSINCOS()
20671 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), in LowerDivRem()
20695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values); in LowerDivRem()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11663 return DAG.getNode(ISD::MERGE_VALUES, dl, {MVT::i128, MVT::Other}, in LowerATOMIC_LOAD_STORE()
12486 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, Carry); in LowerADDSUBO()
12510 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, CarryOp); in LowerADDSUBO_CARRY()
16116 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4222 return DAG.getNode(ISD::MERGE_VALUES, DL, VTs, Sum, OutFlag); in lowerADDSUBO_CARRY()
4248 return DAG.getNode(ISD::MERGE_VALUES, DL, VTs, Value, Overflow); in LowerXALUO()