Searched refs:MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL (Results 1 – 2 of 2) sorted by relevance
3420 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 macro
666 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 macro4585 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); in elink_warpcore_enable_AN_KR()4589 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); in elink_warpcore_enable_AN_KR()4723 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, in elink_warpcore_set_10G_KR()4952 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); in elink_warpcore_set_20G_force_KR2()4956 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); in elink_warpcore_set_20G_force_KR2()