1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _SYS_EFX_REGS_MCDI_AOE_H 29 #define _SYS_EFX_REGS_MCDI_AOE_H 30 31 /***********************************/ 32 /* MC_CMD_FC 33 * Perform an FC operation 34 */ 35 #define MC_CMD_FC 0x9 36 37 /* MC_CMD_FC_IN msgrequest */ 38 #define MC_CMD_FC_IN_LEN 4 39 #define MC_CMD_FC_IN_OP_HDR_OFST 0 40 #define MC_CMD_FC_IN_OP_HDR_LEN 4 41 #define MC_CMD_FC_IN_OP_LBN 0 42 #define MC_CMD_FC_IN_OP_WIDTH 8 43 /* enum: NULL MCDI command to FC. */ 44 #define MC_CMD_FC_OP_NULL 0x1 45 /* enum: Unused opcode */ 46 #define MC_CMD_FC_OP_UNUSED 0x2 47 /* enum: MAC driver commands */ 48 #define MC_CMD_FC_OP_MAC 0x3 49 /* enum: Read FC memory */ 50 #define MC_CMD_FC_OP_READ32 0x4 51 /* enum: Write to FC memory */ 52 #define MC_CMD_FC_OP_WRITE32 0x5 53 /* enum: Read FC memory */ 54 #define MC_CMD_FC_OP_TRC_READ 0x6 55 /* enum: Write to FC memory */ 56 #define MC_CMD_FC_OP_TRC_WRITE 0x7 57 /* enum: FC firmware Version */ 58 #define MC_CMD_FC_OP_GET_VERSION 0x8 59 /* enum: Read FC memory */ 60 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 61 /* enum: Write to FC memory */ 62 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 63 /* enum: SFP parameters */ 64 #define MC_CMD_FC_OP_SFP 0xb 65 /* enum: DDR3 test */ 66 #define MC_CMD_FC_OP_DDR_TEST 0xc 67 /* enum: Get Crash context from FC */ 68 #define MC_CMD_FC_OP_GET_ASSERT 0xd 69 /* enum: Get FPGA Build registers */ 70 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 71 /* enum: Read map support commands */ 72 #define MC_CMD_FC_OP_READ_MAP 0xf 73 /* enum: FC Capabilities */ 74 #define MC_CMD_FC_OP_CAPABILITIES 0x10 75 /* enum: FC Global flags */ 76 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 77 /* enum: FC IO using relative addressing modes */ 78 #define MC_CMD_FC_OP_IO_REL 0x12 79 /* enum: FPGA link information */ 80 #define MC_CMD_FC_OP_UHLINK 0x13 81 /* enum: Configure loopbacks and link on FPGA ports */ 82 #define MC_CMD_FC_OP_SET_LINK 0x14 83 /* enum: Licensing operations relating to AOE */ 84 #define MC_CMD_FC_OP_LICENSE 0x15 85 /* enum: Startup information to the FC */ 86 #define MC_CMD_FC_OP_STARTUP 0x16 87 /* enum: Configure a DMA read */ 88 #define MC_CMD_FC_OP_DMA 0x17 89 /* enum: Configure a timed read */ 90 #define MC_CMD_FC_OP_TIMED_READ 0x18 91 /* enum: Control UART logging */ 92 #define MC_CMD_FC_OP_LOG 0x19 93 /* enum: Get the value of a given clock_id */ 94 #define MC_CMD_FC_OP_CLOCK 0x1a 95 /* enum: DDR3/QDR3 parameters */ 96 #define MC_CMD_FC_OP_DDR 0x1b 97 /* enum: PTP and timestamp control */ 98 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 99 /* enum: Commands for SPI Flash interface */ 100 #define MC_CMD_FC_OP_SPI 0x1d 101 /* enum: Commands for diagnostic components */ 102 #define MC_CMD_FC_OP_DIAG 0x1e 103 /* enum: External AOE port. */ 104 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 105 /* enum: Internal AOE port. */ 106 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 107 108 /* MC_CMD_FC_IN_NULL msgrequest */ 109 #define MC_CMD_FC_IN_NULL_LEN 4 110 #define MC_CMD_FC_IN_CMD_OFST 0 111 #define MC_CMD_FC_IN_CMD_LEN 4 112 113 /* MC_CMD_FC_IN_PHY msgrequest */ 114 #define MC_CMD_FC_IN_PHY_LEN 5 115 /* MC_CMD_FC_IN_CMD_OFST 0 */ 116 /* MC_CMD_FC_IN_CMD_LEN 4 */ 117 /* FC PHY driver operation code */ 118 #define MC_CMD_FC_IN_PHY_OP_OFST 4 119 #define MC_CMD_FC_IN_PHY_OP_LEN 1 120 /* enum: PHY init handler */ 121 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 122 /* enum: PHY reconfigure handler */ 123 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 124 /* enum: PHY reboot handler */ 125 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 126 /* enum: PHY get_supported_cap handler */ 127 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 128 /* enum: PHY get_config handler */ 129 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 130 /* enum: PHY get_media_info handler */ 131 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 132 /* enum: PHY set_led handler */ 133 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 134 /* enum: PHY lasi_interrupt handler */ 135 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 136 /* enum: PHY check_link handler */ 137 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 138 /* enum: PHY fill_stats handler */ 139 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 140 /* enum: PHY bpx_link_state_changed handler */ 141 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 142 /* enum: PHY get_state handler */ 143 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 144 /* enum: PHY start_bist handler */ 145 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 146 /* enum: PHY poll_bist handler */ 147 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 148 /* enum: PHY nvram_test handler */ 149 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 150 /* enum: PHY relinquish handler */ 151 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 152 /* enum: PHY read connection from FC - may be not required */ 153 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 154 /* enum: PHY read flags from FC - may be not required */ 155 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 156 157 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 158 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 159 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 160 #define MC_CMD_FC_IN_PHY_CMD_LEN 4 161 162 /* MC_CMD_FC_IN_MAC msgrequest */ 163 #define MC_CMD_FC_IN_MAC_LEN 8 164 /* MC_CMD_FC_IN_CMD_OFST 0 */ 165 /* MC_CMD_FC_IN_CMD_LEN 4 */ 166 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 167 #define MC_CMD_FC_IN_MAC_HEADER_LEN 4 168 #define MC_CMD_FC_IN_MAC_OP_LBN 0 169 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 170 /* enum: MAC reconfigure handler */ 171 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 172 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 173 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 174 /* enum: MAC statistics */ 175 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 176 /* enum: MAC RX statistics */ 177 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 178 /* enum: MAC TX statistics */ 179 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 180 /* enum: MAC Read status */ 181 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 182 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 183 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 184 /* enum: External FPGA port. */ 185 #define MC_CMD_FC_PORT_EXT 0x0 186 /* enum: Internal Siena-facing FPGA ports. */ 187 #define MC_CMD_FC_PORT_INT 0x1 188 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 189 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 190 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 191 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 192 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 193 * irrelevant. Port number is derived from pci_fn; passed in FC header. 194 */ 195 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 196 /* enum: Override default port number. Port number determined by fields 197 * PORT_TYPE and PORT_IDX. 198 */ 199 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 200 201 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 202 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 203 /* MC_CMD_FC_IN_CMD_OFST 0 */ 204 /* MC_CMD_FC_IN_CMD_LEN 4 */ 205 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 206 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 207 208 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 209 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 210 /* MC_CMD_FC_IN_CMD_OFST 0 */ 211 /* MC_CMD_FC_IN_CMD_LEN 4 */ 212 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 213 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 214 /* MTU size */ 215 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 216 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4 217 /* Drain Tx FIFO */ 218 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 219 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4 220 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 221 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 222 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 223 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 224 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 225 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4 226 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 227 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 228 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 229 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 230 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 231 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4 232 233 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 234 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 235 /* MC_CMD_FC_IN_CMD_OFST 0 */ 236 /* MC_CMD_FC_IN_CMD_LEN 4 */ 237 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 238 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 239 240 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 241 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 242 /* MC_CMD_FC_IN_CMD_OFST 0 */ 243 /* MC_CMD_FC_IN_CMD_LEN 4 */ 244 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 245 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 246 247 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 248 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 249 /* MC_CMD_FC_IN_CMD_OFST 0 */ 250 /* MC_CMD_FC_IN_CMD_LEN 4 */ 251 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 252 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 253 254 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 255 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 256 /* MC_CMD_FC_IN_CMD_OFST 0 */ 257 /* MC_CMD_FC_IN_CMD_LEN 4 */ 258 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 259 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 260 /* MC Statistics index */ 261 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 262 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4 263 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 264 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4 265 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 266 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 267 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 268 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 269 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 270 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 271 /* Number of statistics to read */ 272 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 273 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4 274 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 275 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 276 277 /* MC_CMD_FC_IN_READ32 msgrequest */ 278 #define MC_CMD_FC_IN_READ32_LEN 16 279 /* MC_CMD_FC_IN_CMD_OFST 0 */ 280 /* MC_CMD_FC_IN_CMD_LEN 4 */ 281 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 282 #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4 283 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 284 #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4 285 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 286 #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4 287 288 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 289 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 290 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 291 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 292 /* MC_CMD_FC_IN_CMD_OFST 0 */ 293 /* MC_CMD_FC_IN_CMD_LEN 4 */ 294 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 295 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4 296 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 297 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4 298 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 299 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 300 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 301 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 302 303 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 304 #define MC_CMD_FC_IN_TRC_READ_LEN 12 305 /* MC_CMD_FC_IN_CMD_OFST 0 */ 306 /* MC_CMD_FC_IN_CMD_LEN 4 */ 307 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 308 #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4 309 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 310 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4 311 312 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 313 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 314 /* MC_CMD_FC_IN_CMD_OFST 0 */ 315 /* MC_CMD_FC_IN_CMD_LEN 4 */ 316 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 317 #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4 318 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 319 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4 320 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 321 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 322 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 323 324 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 325 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 326 /* MC_CMD_FC_IN_CMD_OFST 0 */ 327 /* MC_CMD_FC_IN_CMD_LEN 4 */ 328 329 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 330 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 331 /* MC_CMD_FC_IN_CMD_OFST 0 */ 332 /* MC_CMD_FC_IN_CMD_LEN 4 */ 333 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 334 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4 335 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 336 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4 337 338 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 339 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 340 /* MC_CMD_FC_IN_CMD_OFST 0 */ 341 /* MC_CMD_FC_IN_CMD_LEN 4 */ 342 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 343 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4 344 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 345 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4 346 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 347 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 348 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 349 350 /* MC_CMD_FC_IN_SFP msgrequest */ 351 #define MC_CMD_FC_IN_SFP_LEN 28 352 /* MC_CMD_FC_IN_CMD_OFST 0 */ 353 /* MC_CMD_FC_IN_CMD_LEN 4 */ 354 /* Link speed is 100, 1000, 10000, 40000 */ 355 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 356 #define MC_CMD_FC_IN_SFP_SPEED_LEN 4 357 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 358 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 359 #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4 360 /* Not relevant for cards with QSFP modules. For older cards, true if module is 361 * a dual speed SFP+ module. 362 */ 363 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 364 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4 365 /* True if an SFP Module is present (other fields valid when true) */ 366 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 367 #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4 368 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 369 * is unused and the type is communicated by other means. 370 */ 371 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 372 #define MC_CMD_FC_IN_SFP_TYPE_LEN 4 373 /* Capabilities corresponding to 1 bits. */ 374 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 375 #define MC_CMD_FC_IN_SFP_CAPS_LEN 4 376 377 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 378 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 379 /* MC_CMD_FC_IN_CMD_OFST 0 */ 380 /* MC_CMD_FC_IN_CMD_LEN 4 */ 381 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 382 #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 383 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 384 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 385 /* enum: DRAM Test Start */ 386 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 387 /* enum: DRAM Test Poll */ 388 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 389 390 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 391 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 392 /* MC_CMD_FC_IN_CMD_OFST 0 */ 393 /* MC_CMD_FC_IN_CMD_LEN 4 */ 394 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 395 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 396 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 397 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4 398 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 399 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 400 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 401 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 402 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 403 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 404 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 405 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 406 407 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 408 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 409 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 410 #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4 411 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 412 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 413 /* Clear previous test result and prepare for restarting DDR test */ 414 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 415 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4 416 417 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 418 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 419 /* MC_CMD_FC_IN_CMD_OFST 0 */ 420 /* MC_CMD_FC_IN_CMD_LEN 4 */ 421 422 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 423 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 424 /* MC_CMD_FC_IN_CMD_OFST 0 */ 425 /* MC_CMD_FC_IN_CMD_LEN 4 */ 426 /* FPGA build info operation code */ 427 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 428 #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4 429 /* enum: Get the build registers */ 430 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 431 /* enum: Get the services registers */ 432 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 433 /* enum: Get the BSP version */ 434 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 435 /* enum: Get build register for V2 (SFA974X) */ 436 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 437 /* enum: GEt the services register for V2 (SFA974X) */ 438 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 439 440 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 441 #define MC_CMD_FC_IN_READ_MAP_LEN 8 442 /* MC_CMD_FC_IN_CMD_OFST 0 */ 443 /* MC_CMD_FC_IN_CMD_LEN 4 */ 444 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 445 #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 446 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 447 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 448 /* enum: Get the number of map regions */ 449 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 450 /* enum: Get the specified map */ 451 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 452 453 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 454 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 455 /* MC_CMD_FC_IN_CMD_OFST 0 */ 456 /* MC_CMD_FC_IN_CMD_LEN 4 */ 457 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 458 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 459 460 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 461 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 462 /* MC_CMD_FC_IN_CMD_OFST 0 */ 463 /* MC_CMD_FC_IN_CMD_LEN 4 */ 464 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 465 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 466 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 467 #define MC_CMD_FC_IN_MAP_INDEX_LEN 4 468 469 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 470 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 471 /* MC_CMD_FC_IN_CMD_OFST 0 */ 472 /* MC_CMD_FC_IN_CMD_LEN 4 */ 473 474 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 475 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 476 /* MC_CMD_FC_IN_CMD_OFST 0 */ 477 /* MC_CMD_FC_IN_CMD_LEN 4 */ 478 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 479 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4 480 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 481 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 482 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 483 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 484 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 485 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 486 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 487 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 488 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 489 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 490 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 491 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 492 493 /* MC_CMD_FC_IN_IO_REL msgrequest */ 494 #define MC_CMD_FC_IN_IO_REL_LEN 8 495 /* MC_CMD_FC_IN_CMD_OFST 0 */ 496 /* MC_CMD_FC_IN_CMD_LEN 4 */ 497 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 498 #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 499 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 500 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 501 /* enum: Get the base address that the FC applies to relative commands */ 502 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 503 /* enum: Read data */ 504 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 505 /* enum: Write data */ 506 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 507 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 508 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 509 /* enum: Application address space */ 510 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 511 /* enum: Flash address space */ 512 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 513 514 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 515 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 516 /* MC_CMD_FC_IN_CMD_OFST 0 */ 517 /* MC_CMD_FC_IN_CMD_LEN 4 */ 518 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 519 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 520 521 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 522 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 523 /* MC_CMD_FC_IN_CMD_OFST 0 */ 524 /* MC_CMD_FC_IN_CMD_LEN 4 */ 525 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 526 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 527 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 528 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4 529 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 530 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4 531 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 532 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4 533 534 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 535 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 536 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 537 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 538 /* MC_CMD_FC_IN_CMD_OFST 0 */ 539 /* MC_CMD_FC_IN_CMD_LEN 4 */ 540 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 541 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 542 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 543 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4 544 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 545 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4 546 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 547 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 548 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 549 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 550 551 /* MC_CMD_FC_IN_UHLINK msgrequest */ 552 #define MC_CMD_FC_IN_UHLINK_LEN 8 553 /* MC_CMD_FC_IN_CMD_OFST 0 */ 554 /* MC_CMD_FC_IN_CMD_LEN 4 */ 555 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 556 #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 557 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 558 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 559 /* enum: Get PHY configuration info */ 560 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 561 /* enum: Get MAC configuration info */ 562 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 563 /* enum: Get Rx eye table */ 564 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 565 /* enum: Get Rx eye plot */ 566 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 567 /* enum: Get Rx eye plot */ 568 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 569 /* enum: Retune Rx settings */ 570 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 571 /* enum: Set loopback mode on fpga port */ 572 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 573 /* enum: Get loopback mode config state on fpga port */ 574 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 575 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 576 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 577 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 578 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 579 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 580 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 581 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 582 * irrelevant. Port number is derived from pci_fn; passed in FC header. 583 */ 584 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 585 /* enum: Override default port number. Port number determined by fields 586 * PORT_TYPE and PORT_IDX. 587 */ 588 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 589 590 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 591 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 592 /* MC_CMD_FC_IN_CMD_OFST 0 */ 593 /* MC_CMD_FC_IN_CMD_LEN 4 */ 594 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 595 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 596 597 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 598 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 599 /* MC_CMD_FC_IN_CMD_OFST 0 */ 600 /* MC_CMD_FC_IN_CMD_LEN 4 */ 601 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 602 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 603 604 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 605 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 606 /* MC_CMD_FC_IN_CMD_OFST 0 */ 607 /* MC_CMD_FC_IN_CMD_LEN 4 */ 608 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 609 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 610 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 611 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4 612 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 613 614 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 615 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 616 /* MC_CMD_FC_IN_CMD_OFST 0 */ 617 /* MC_CMD_FC_IN_CMD_LEN 4 */ 618 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 619 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 620 621 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 622 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 623 /* MC_CMD_FC_IN_CMD_OFST 0 */ 624 /* MC_CMD_FC_IN_CMD_LEN 4 */ 625 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 626 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 627 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 628 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4 629 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 630 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4 631 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 632 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4 633 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 634 635 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 636 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 637 /* MC_CMD_FC_IN_CMD_OFST 0 */ 638 /* MC_CMD_FC_IN_CMD_LEN 4 */ 639 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 640 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 641 642 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 643 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 644 /* MC_CMD_FC_IN_CMD_OFST 0 */ 645 /* MC_CMD_FC_IN_CMD_LEN 4 */ 646 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 647 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 648 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 649 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4 650 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 651 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 652 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 653 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 654 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4 655 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 656 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 657 658 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 659 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 660 /* MC_CMD_FC_IN_CMD_OFST 0 */ 661 /* MC_CMD_FC_IN_CMD_LEN 4 */ 662 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 663 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 664 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 665 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4 666 667 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 668 #define MC_CMD_FC_IN_SET_LINK_LEN 16 669 /* MC_CMD_FC_IN_CMD_OFST 0 */ 670 /* MC_CMD_FC_IN_CMD_LEN 4 */ 671 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 672 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 673 #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4 674 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 675 #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4 676 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 677 #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4 678 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 679 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 680 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 681 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 682 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 683 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 684 685 /* MC_CMD_FC_IN_LICENSE msgrequest */ 686 #define MC_CMD_FC_IN_LICENSE_LEN 8 687 /* MC_CMD_FC_IN_CMD_OFST 0 */ 688 /* MC_CMD_FC_IN_CMD_LEN 4 */ 689 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 690 #define MC_CMD_FC_IN_LICENSE_OP_LEN 4 691 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 692 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 693 694 /* MC_CMD_FC_IN_STARTUP msgrequest */ 695 #define MC_CMD_FC_IN_STARTUP_LEN 40 696 /* MC_CMD_FC_IN_CMD_OFST 0 */ 697 /* MC_CMD_FC_IN_CMD_LEN 4 */ 698 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 699 #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4 700 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 701 #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4 702 /* Length of identifier */ 703 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 704 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4 705 /* Identifier for AOE FPGA */ 706 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 707 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 708 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 709 710 /* MC_CMD_FC_IN_DMA msgrequest */ 711 #define MC_CMD_FC_IN_DMA_LEN 8 712 /* MC_CMD_FC_IN_CMD_OFST 0 */ 713 /* MC_CMD_FC_IN_CMD_LEN 4 */ 714 #define MC_CMD_FC_IN_DMA_OP_OFST 4 715 #define MC_CMD_FC_IN_DMA_OP_LEN 4 716 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 717 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 718 719 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 720 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 721 /* MC_CMD_FC_IN_CMD_OFST 0 */ 722 /* MC_CMD_FC_IN_CMD_LEN 4 */ 723 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 724 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 725 /* FC supplied handle */ 726 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 727 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4 728 729 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 730 #define MC_CMD_FC_IN_DMA_READ_LEN 16 731 /* MC_CMD_FC_IN_CMD_OFST 0 */ 732 /* MC_CMD_FC_IN_CMD_LEN 4 */ 733 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 734 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 735 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 736 #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4 737 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 738 #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4 739 740 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 741 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 742 /* MC_CMD_FC_IN_CMD_OFST 0 */ 743 /* MC_CMD_FC_IN_CMD_LEN 4 */ 744 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 745 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 746 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 747 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 748 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 749 750 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 751 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 752 /* MC_CMD_FC_IN_CMD_OFST 0 */ 753 /* MC_CMD_FC_IN_CMD_LEN 4 */ 754 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 755 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 756 /* Host supplied handle (unique) */ 757 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 758 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4 759 /* Address into which to transfer data in host */ 760 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 761 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 762 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 763 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 764 /* AOE address from which to transfer data */ 765 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 766 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 767 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 768 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 769 /* Length of AOE transfer (total) */ 770 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 771 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4 772 /* Length of host transfer (total) */ 773 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 774 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4 775 /* Offset back from aoe_address to apply operation to */ 776 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 777 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4 778 /* Data to apply at offset */ 779 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 780 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4 781 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 782 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4 783 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 784 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 785 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 786 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 787 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 788 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 789 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 790 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 791 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 792 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 793 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 794 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 795 /* Period at which reads are performed (100ms units) */ 796 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 797 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 798 799 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 800 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 801 /* MC_CMD_FC_IN_CMD_OFST 0 */ 802 /* MC_CMD_FC_IN_CMD_LEN 4 */ 803 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 804 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 805 /* FC supplied handle */ 806 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 807 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4 808 809 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 810 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 811 /* MC_CMD_FC_IN_CMD_OFST 0 */ 812 /* MC_CMD_FC_IN_CMD_LEN 4 */ 813 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 814 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 815 /* FC supplied handle */ 816 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 817 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4 818 819 /* MC_CMD_FC_IN_LOG msgrequest */ 820 #define MC_CMD_FC_IN_LOG_LEN 8 821 /* MC_CMD_FC_IN_CMD_OFST 0 */ 822 /* MC_CMD_FC_IN_CMD_LEN 4 */ 823 #define MC_CMD_FC_IN_LOG_OP_OFST 4 824 #define MC_CMD_FC_IN_LOG_OP_LEN 4 825 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 826 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 827 828 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 829 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 830 /* MC_CMD_FC_IN_CMD_OFST 0 */ 831 /* MC_CMD_FC_IN_CMD_LEN 4 */ 832 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 833 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 834 /* Partition offset into flash */ 835 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 836 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4 837 /* Partition length */ 838 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 839 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4 840 /* Partition erase size */ 841 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 842 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4 843 844 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 845 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 846 /* MC_CMD_FC_IN_CMD_OFST 0 */ 847 /* MC_CMD_FC_IN_CMD_LEN 4 */ 848 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 849 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 850 /* Enable/disable printing to JTAG UART */ 851 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 852 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 853 854 /* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ 855 #define MC_CMD_FC_IN_CLOCK_LEN 12 856 /* MC_CMD_FC_IN_CMD_OFST 0 */ 857 /* MC_CMD_FC_IN_CMD_LEN 4 */ 858 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 859 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4 860 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 861 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 862 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 863 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4 864 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 865 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 866 867 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the 868 * specified clock 869 */ 870 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 871 /* MC_CMD_FC_IN_CMD_OFST 0 */ 872 /* MC_CMD_FC_IN_CMD_LEN 4 */ 873 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 874 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 875 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 876 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 877 878 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified 879 * clock 880 */ 881 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 882 /* MC_CMD_FC_IN_CMD_OFST 0 */ 883 /* MC_CMD_FC_IN_CMD_LEN 4 */ 884 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 885 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 886 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 887 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 888 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 889 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 890 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 891 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 892 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 893 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 894 895 /* MC_CMD_FC_IN_DDR msgrequest */ 896 #define MC_CMD_FC_IN_DDR_LEN 12 897 /* MC_CMD_FC_IN_CMD_OFST 0 */ 898 /* MC_CMD_FC_IN_CMD_LEN 4 */ 899 #define MC_CMD_FC_IN_DDR_OP_OFST 4 900 #define MC_CMD_FC_IN_DDR_OP_LEN 4 901 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 902 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 903 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 904 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 905 #define MC_CMD_FC_IN_DDR_BANK_LEN 4 906 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 907 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 908 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 909 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 910 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 911 912 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 913 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 914 /* MC_CMD_FC_IN_CMD_OFST 0 */ 915 /* MC_CMD_FC_IN_CMD_LEN 4 */ 916 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 917 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 918 /* Affected bank */ 919 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 920 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 921 /* Flags */ 922 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 923 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 924 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 925 /* 128-byte page of serial presence detect data read from module's EEPROM */ 926 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 927 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 928 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 929 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 930 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 931 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4 932 933 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 934 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 935 /* MC_CMD_FC_IN_CMD_OFST 0 */ 936 /* MC_CMD_FC_IN_CMD_LEN 4 */ 937 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 938 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 939 /* Affected bank */ 940 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 941 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 942 /* Size of DDR */ 943 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 944 #define MC_CMD_FC_IN_DDR_SIZE_LEN 4 945 946 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 947 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 948 /* MC_CMD_FC_IN_CMD_OFST 0 */ 949 /* MC_CMD_FC_IN_CMD_LEN 4 */ 950 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 951 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 952 /* Affected bank */ 953 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 954 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 955 956 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 957 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 958 /* MC_CMD_FC_IN_CMD_OFST 0 */ 959 /* MC_CMD_FC_IN_CMD_LEN 4 */ 960 /* FC timestamp operation code */ 961 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 962 #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4 963 /* enum: Read transmit timestamp(s) */ 964 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 965 /* enum: Read snapshot timestamps */ 966 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 967 /* enum: Clear all transmit timestamps */ 968 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 969 970 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 971 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 972 /* MC_CMD_FC_IN_CMD_OFST 0 */ 973 /* MC_CMD_FC_IN_CMD_LEN 4 */ 974 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 975 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4 976 /* Control filtering of the returned timestamp and sequence number specified 977 * here 978 */ 979 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 980 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4 981 /* enum: Return most recent timestamp. No filtering */ 982 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 983 /* enum: Match timestamp against the PTP clock ID, port number and sequence 984 * number specified 985 */ 986 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 987 /* Clock identity of PTP packet for which timestamp required */ 988 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 989 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 990 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 991 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 992 /* Port number of PTP packet for which timestamp required */ 993 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 994 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4 995 /* Sequence number of PTP packet for which timestamp required */ 996 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 997 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4 998 999 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1000 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1001 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1002 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1003 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1004 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4 1005 1006 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1007 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1008 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1009 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1010 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1011 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4 1012 1013 /* MC_CMD_FC_IN_SPI msgrequest */ 1014 #define MC_CMD_FC_IN_SPI_LEN 8 1015 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1016 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1017 /* Basic commands for SPI Flash. */ 1018 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1019 #define MC_CMD_FC_IN_SPI_OP_LEN 4 1020 /* enum: SPI Flash read */ 1021 #define MC_CMD_FC_IN_SPI_READ 0x0 1022 /* enum: SPI Flash write */ 1023 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1024 /* enum: SPI Flash erase */ 1025 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1026 1027 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1028 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1029 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1030 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1031 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1032 #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4 1033 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1034 #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4 1035 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1036 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4 1037 1038 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1039 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1040 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1041 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1042 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1043 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1044 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1045 #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4 1046 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1047 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4 1048 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1049 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1050 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1051 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1052 1053 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1054 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1055 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1056 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1057 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1058 #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4 1059 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1060 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4 1061 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1062 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4 1063 1064 /* MC_CMD_FC_IN_DIAG msgrequest */ 1065 #define MC_CMD_FC_IN_DIAG_LEN 8 1066 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1067 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1068 /* Operation code indicating component type */ 1069 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1070 #define MC_CMD_FC_IN_DIAG_OP_LEN 4 1071 /* enum: Power noise generator. */ 1072 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1073 /* enum: DDR soak test component. */ 1074 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1075 /* enum: Diagnostics datapath control component. */ 1076 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1077 1078 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1079 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1080 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1081 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1082 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1083 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4 1084 /* Sub-opcode describing the operation to be carried out */ 1085 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1086 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4 1087 /* enum: Read the configuration (the 32-bit values in each of the clock enable 1088 * count and toggle count registers) 1089 */ 1090 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1091 /* enum: Write a new configuration to the clock enable count and toggle count 1092 * registers 1093 */ 1094 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1095 1096 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1097 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1098 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1099 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1100 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 1101 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4 1102 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 1103 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4 1104 1105 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 1106 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 1107 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1108 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1109 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 1110 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4 1111 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 1112 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4 1113 /* The 32-bit value to be written to the toggle count register */ 1114 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 1115 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4 1116 /* The 32-bit value to be written to the clock enable count register */ 1117 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 1118 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4 1119 1120 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 1121 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 1122 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1123 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1124 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 1125 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4 1126 /* Sub-opcode describing the operation to be carried out */ 1127 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 1128 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4 1129 /* enum: Starts DDR soak test on selected banks */ 1130 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 1131 /* enum: Read status of DDR soak test */ 1132 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 1133 /* enum: Stop test */ 1134 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 1135 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 1136 * tests to fail until the bit is cleared. 1137 */ 1138 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 1139 1140 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 1141 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 1142 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1143 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1144 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 1145 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4 1146 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 1147 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4 1148 /* Mask of DDR banks to be tested */ 1149 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 1150 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4 1151 /* Pattern to use in the soak test */ 1152 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 1153 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4 1154 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 1155 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 1156 /* Either multiple automatic tests until a STOP command is issued, or one 1157 * single test 1158 */ 1159 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 1160 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4 1161 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 1162 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 1163 1164 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 1165 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 1166 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1167 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1168 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 1169 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4 1170 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 1171 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4 1172 /* DDR bank to read status from */ 1173 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 1174 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4 1175 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 1176 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 1177 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 1178 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 1179 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 1180 1181 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 1182 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 1183 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1184 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1185 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 1186 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4 1187 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 1188 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4 1189 /* Mask of DDR banks to be tested */ 1190 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 1191 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4 1192 1193 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 1194 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 1195 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1196 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1197 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 1198 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4 1199 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 1200 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4 1201 /* Mask of DDR banks to set/clear error flag on */ 1202 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 1203 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4 1204 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 1205 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4 1206 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 1207 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 1208 1209 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 1210 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 1211 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1212 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1213 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 1214 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4 1215 /* Sub-opcode describing the operation to be carried out */ 1216 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 1217 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4 1218 /* enum: Set a known datapath configuration */ 1219 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 1220 /* enum: Apply raw config to datapath control registers */ 1221 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 1222 1223 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 1224 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 1225 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1226 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1227 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 1228 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4 1229 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 1230 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4 1231 /* Datapath configuration identifier */ 1232 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 1233 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4 1234 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 1235 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 1236 1237 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 1238 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 1239 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1240 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1241 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 1242 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4 1243 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 1244 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4 1245 /* Value to write into control register 1 */ 1246 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 1247 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4 1248 /* Value to write into control register 2 */ 1249 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 1250 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4 1251 /* Value to write into control register 3 */ 1252 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 1253 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4 1254 1255 /* MC_CMD_FC_OUT msgresponse */ 1256 #define MC_CMD_FC_OUT_LEN 0 1257 1258 /* MC_CMD_FC_OUT_NULL msgresponse */ 1259 #define MC_CMD_FC_OUT_NULL_LEN 0 1260 1261 /* MC_CMD_FC_OUT_READ32 msgresponse */ 1262 #define MC_CMD_FC_OUT_READ32_LENMIN 4 1263 #define MC_CMD_FC_OUT_READ32_LENMAX 252 1264 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 1265 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 1266 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 1267 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 1268 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 1269 1270 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 1271 #define MC_CMD_FC_OUT_WRITE32_LEN 0 1272 1273 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 1274 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 1275 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 1276 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 1277 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 1278 1279 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 1280 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 1281 1282 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 1283 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 1284 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 1285 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4 1286 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 1287 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 1288 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 1289 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 1290 1291 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 1292 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 1293 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 1294 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 1295 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 1296 1297 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 1298 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 1299 1300 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 1301 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 1302 1303 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 1304 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 1305 1306 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 1307 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 1308 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 1309 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4 1310 1311 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 1312 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 1313 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 1314 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 1315 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 1316 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 1317 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 1318 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 1319 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 1320 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 1321 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1322 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 1323 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 1324 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 1325 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 1326 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 1327 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 1328 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 1329 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 1330 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 1331 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1332 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 1333 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 1334 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 1335 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 1336 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 1337 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 1338 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 1339 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 1340 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 1341 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 1342 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 1343 /* enum: (Last entry) */ 1344 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 1345 1346 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 1347 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 1348 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 1349 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 1350 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 1351 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 1352 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 1353 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 1354 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 1355 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 1356 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1357 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 1358 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 1359 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 1360 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 1361 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 1362 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 1363 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 1364 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 1365 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 1366 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1367 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 1368 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 1369 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 1370 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 1371 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 1372 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 1373 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 1374 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 1375 /* enum: (Last entry) */ 1376 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 1377 1378 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 1379 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 1380 /* MAC Statistics */ 1381 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 1382 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 1383 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 1384 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 1385 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 1386 1387 /* MC_CMD_FC_OUT_MAC msgresponse */ 1388 #define MC_CMD_FC_OUT_MAC_LEN 0 1389 1390 /* MC_CMD_FC_OUT_SFP msgresponse */ 1391 #define MC_CMD_FC_OUT_SFP_LEN 0 1392 1393 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 1394 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 1395 1396 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 1397 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 1398 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 1399 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4 1400 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 1401 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 1402 /* enum: Test not yet initiated */ 1403 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 1404 /* enum: Test is in progress */ 1405 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 1406 /* enum: Timed completed */ 1407 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 1408 /* enum: Test did not complete in specified time */ 1409 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 1410 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 1411 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 1412 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 1413 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 1414 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 1415 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 1416 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 1417 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 1418 /* Test result from FPGA */ 1419 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 1420 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4 1421 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 1422 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 1423 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 1424 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 1425 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 1426 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 1427 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 1428 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 1429 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 1430 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 1431 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 1432 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 1433 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 1434 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 1435 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 1436 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 1437 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 1438 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 1439 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 1440 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 1441 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 1442 1443 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 1444 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 1445 1446 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 1447 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 1448 /* Assertion status flag. */ 1449 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 1450 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4 1451 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 1452 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 1453 /* enum: No crash data available */ 1454 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 1455 /* enum: New crash data available */ 1456 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 1457 /* enum: Crash data has been sent */ 1458 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 1459 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 1460 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 1461 /* enum: No crash has been recorded. */ 1462 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 1463 /* enum: Crash due to exception. */ 1464 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 1465 /* enum: Crash due to assertion. */ 1466 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 1467 /* Failing PC value */ 1468 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 1469 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4 1470 /* Saved GP regs */ 1471 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 1472 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 1473 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 1474 /* Exception Type */ 1475 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 1476 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4 1477 /* Instruction at which exception occurred */ 1478 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 1479 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4 1480 /* BAD Address that triggered address-based exception */ 1481 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 1482 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4 1483 1484 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 1485 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 1486 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 1487 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4 1488 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 1489 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 1490 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 1491 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 1492 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 1493 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 1494 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 1495 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 1496 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 1497 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 1498 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 1499 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 1500 /* Build timestamp (seconds since epoch) */ 1501 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 1502 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4 1503 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 1504 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4 1505 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 1506 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 1507 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 1508 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 1509 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 1510 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 1511 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 1512 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 1513 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 1514 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 1515 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 1516 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 1517 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 1518 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 1519 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 1520 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 1521 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 1522 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 1523 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 1524 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 1525 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 1526 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 1527 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 1528 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 1529 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 1530 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 1531 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 1532 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 1533 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 1534 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 1535 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 1536 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 1537 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 1538 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4 1539 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 1540 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 1541 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 1542 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 1543 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 1544 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 1545 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 1546 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 1547 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 1548 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4 1549 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 1550 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1551 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 1552 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1553 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 1554 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4 1555 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 1556 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1557 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 1558 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1559 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 1560 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 1561 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 1562 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 1563 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 1564 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4 1565 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 1566 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4 1567 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 1568 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 1569 1570 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 1571 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 1572 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 1573 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4 1574 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 1575 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 1576 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 1577 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 1578 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 1579 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 1580 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 1581 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 1582 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 1583 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 1584 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 1585 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 1586 /* Build timestamp (seconds since epoch) */ 1587 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 1588 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4 1589 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 1590 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4 1591 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 1592 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 1593 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 1594 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 1595 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 1596 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 1597 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 1598 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 1599 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 1600 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 1601 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 1602 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 1603 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 1604 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 1605 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 1606 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 1607 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 1608 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 1609 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 1610 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 1611 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 1612 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 1613 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 1614 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 1615 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 1616 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 1617 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 1618 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 1619 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 1620 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 1621 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 1622 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 1623 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 1624 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 1625 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 1626 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 1627 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 1628 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 1629 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 1630 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 1631 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 1632 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 1633 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 1634 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 1635 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 1636 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 1637 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 1638 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 1639 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 1640 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 1641 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 1642 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 1643 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 1644 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 1645 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 1646 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 1647 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 1648 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 1649 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 1650 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 1651 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 1652 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 1653 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 1654 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 1655 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 1656 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 1657 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 1658 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 1659 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 1660 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 1661 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 1662 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4 1663 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 1664 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 1665 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 1666 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 1667 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1668 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1669 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 1670 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4 1671 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 1672 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1673 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 1674 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1675 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 1676 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4 1677 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 1678 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1679 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 1680 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1681 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 1682 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4 1683 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 1684 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4 1685 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 1686 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 1687 1688 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 1689 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 1690 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 1691 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4 1692 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 1693 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 1694 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 1695 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 1696 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 1697 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 1698 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 1699 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 1700 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 1701 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 1702 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 1703 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 1704 /* Build timestamp (seconds since epoch) */ 1705 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 1706 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4 1707 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 1708 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4 1709 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 1710 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 1711 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 1712 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 1713 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 1714 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 1715 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 1716 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 1717 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 1718 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 1719 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 1720 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 1721 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 1722 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4 1723 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 1724 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 1725 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 1726 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 1727 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 1728 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4 1729 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 1730 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 1731 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 1732 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 1733 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 1734 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4 1735 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 1736 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 1737 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 1738 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 1739 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 1740 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4 1741 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 1742 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4 1743 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 1744 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 1745 1746 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 1747 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 1748 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 1749 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4 1750 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 1751 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 1752 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 1753 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 1754 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 1755 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 1756 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 1757 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 1758 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 1759 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 1760 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 1761 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 1762 /* Build timestamp (seconds since epoch) */ 1763 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 1764 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4 1765 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 1766 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4 1767 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 1768 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 1769 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 1770 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 1771 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 1772 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4 1773 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 1774 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 1775 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 1776 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 1777 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1778 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1779 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 1780 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4 1781 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 1782 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4 1783 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 1784 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 1785 1786 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 1787 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 1788 /* Qsys system ID */ 1789 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 1790 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4 1791 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 1792 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 1793 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 1794 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 1795 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 1796 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 1797 1798 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 1799 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 1800 /* Number of maps */ 1801 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 1802 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4 1803 1804 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 1805 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 1806 /* Index of the map */ 1807 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 1808 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4 1809 /* Options for the map */ 1810 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 1811 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 1812 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 1813 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 1814 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 1815 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 1816 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 1817 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 1818 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 1819 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 1820 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 1821 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 1822 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 1823 /* Address of start of map */ 1824 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 1825 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 1826 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 1827 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 1828 /* Length of address map */ 1829 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 1830 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 1831 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 1832 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 1833 /* Component information field */ 1834 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 1835 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4 1836 /* License expiry data for map */ 1837 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 1838 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 1839 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 1840 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 1841 /* Name of the component */ 1842 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 1843 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 1844 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 1845 1846 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 1847 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 1848 1849 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 1850 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 1851 /* Number of internal ports */ 1852 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 1853 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4 1854 /* Number of external ports */ 1855 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 1856 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4 1857 1858 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 1859 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 1860 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 1861 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4 1862 1863 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 1864 #define MC_CMD_FC_OUT_IO_REL_LEN 0 1865 1866 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 1867 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 1868 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 1869 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4 1870 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 1871 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4 1872 1873 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 1874 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 1875 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 1876 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 1877 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 1878 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 1879 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 1880 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 1881 1882 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 1883 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 1884 1885 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 1886 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 1887 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 1888 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4 1889 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 1890 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 1891 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 1892 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 1893 /* Transceiver Transmit settings */ 1894 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 1895 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4 1896 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 1897 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 1898 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 1899 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 1900 /* Transceiver Receive settings */ 1901 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 1902 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4 1903 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 1904 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 1905 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 1906 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 1907 /* Rx eye opening */ 1908 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 1909 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4 1910 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 1911 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 1912 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 1913 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 1914 /* PCS status word */ 1915 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 1916 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4 1917 /* Link status word */ 1918 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 1919 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4 1920 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 1921 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 1922 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 1923 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 1924 /* Current SFp parameters applied */ 1925 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 1926 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 1927 /* Link speed is 100, 1000, 10000 */ 1928 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 1929 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4 1930 /* Length of copper cable - zero when not relevant */ 1931 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 1932 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4 1933 /* True if a dual speed SFP+ module */ 1934 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 1935 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4 1936 /* True if an SFP Module is present (other fields valid when true) */ 1937 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 1938 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4 1939 /* The type of the SFP+ Module */ 1940 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 1941 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4 1942 /* PHY config flags */ 1943 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 1944 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4 1945 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 1946 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 1947 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 1948 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 1949 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 1950 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 1951 1952 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 1953 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 1954 /* MAC configuration applied */ 1955 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 1956 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4 1957 /* MTU size */ 1958 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 1959 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4 1960 /* IF Mode status */ 1961 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 1962 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4 1963 /* MAC address configured */ 1964 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 1965 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 1966 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 1967 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 1968 1969 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 1970 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 1971 /* Rx Eye measurements */ 1972 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 1973 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 1974 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 1975 1976 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 1977 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 1978 1979 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 1980 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 1981 /* Has the eye plot dump completed and data returned is valid? */ 1982 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 1983 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4 1984 /* Rx Eye binary plot */ 1985 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 1986 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 1987 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 1988 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 1989 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 1990 1991 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 1992 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 1993 1994 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 1995 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 1996 1997 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 1998 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 1999 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2000 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4 2001 2002 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2003 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2004 2005 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2006 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2007 2008 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2009 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2010 /* Count of valid keys */ 2011 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2012 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4 2013 /* Count of invalid keys */ 2014 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2015 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4 2016 /* Count of blacklisted keys */ 2017 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2018 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4 2019 2020 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2021 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2022 /* Capabilities of the FPGA/FC */ 2023 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2024 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4 2025 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2026 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2027 2028 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2029 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2030 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2031 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2032 /* The data read */ 2033 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2034 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2035 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2036 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2037 2038 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2039 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2040 /* Timer handle */ 2041 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2042 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4 2043 2044 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2045 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2046 /* Host supplied handle (unique) */ 2047 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2048 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4 2049 /* Address into which to transfer data in host */ 2050 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2051 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2052 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2053 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2054 /* AOE address from which to transfer data */ 2055 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2056 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2057 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2058 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2059 /* Length of AOE transfer (total) */ 2060 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2061 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4 2062 /* Length of host transfer (total) */ 2063 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2064 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4 2065 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2066 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2067 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4 2068 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2069 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4 2070 /* When active, start read time */ 2071 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2072 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2073 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2074 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2075 /* When active, end read time */ 2076 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2077 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2078 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2079 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2080 2081 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2082 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2083 2084 /* MC_CMD_FC_OUT_LOG msgresponse */ 2085 #define MC_CMD_FC_OUT_LOG_LEN 0 2086 2087 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2088 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2089 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2090 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4 2091 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2092 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2093 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2094 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2095 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2096 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4 2097 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2098 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4 2099 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2100 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4 2101 2102 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2103 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2104 2105 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2106 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2107 2108 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2109 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2110 2111 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2112 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2113 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2114 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4 2115 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2116 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2117 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2118 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2119 2120 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2121 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2122 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2123 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4 2124 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2125 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4 2126 2127 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2128 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2129 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2130 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2131 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2132 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 2133 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2134 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4 2135 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2136 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2137 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2138 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2139 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2140 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2141 2142 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2143 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2144 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2145 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2146 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2147 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2148 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2149 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2150 2151 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2152 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2153 2154 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2155 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2156 2157 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2158 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2159 /* The 32-bit value read from the toggle count register */ 2160 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2161 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4 2162 /* The 32-bit value read from the clock enable count register */ 2163 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2164 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4 2165 2166 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2167 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2168 2169 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2170 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2171 2172 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2173 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2174 /* DDR soak test status word; bits [4:0] are relevant. */ 2175 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2176 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4 2177 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2178 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2179 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2180 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2181 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2182 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2183 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2184 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2185 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2186 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2187 /* DDR soak test error count */ 2188 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2189 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4 2190 2191 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2192 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2193 2194 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2195 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2196 2197 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2198 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2199 2200 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2201 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2202 2203 /***********************************/ 2204 /* MC_CMD_AOE 2205 * AOE operations on MC 2206 */ 2207 #define MC_CMD_AOE 0xa 2208 2209 /* MC_CMD_AOE_IN msgrequest */ 2210 #define MC_CMD_AOE_IN_LEN 4 2211 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2212 #define MC_CMD_AOE_IN_OP_HDR_LEN 4 2213 #define MC_CMD_AOE_IN_OP_LBN 0 2214 #define MC_CMD_AOE_IN_OP_WIDTH 8 2215 /* enum: FPGA and CPLD information */ 2216 #define MC_CMD_AOE_OP_INFO 0x1 2217 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2218 #define MC_CMD_AOE_OP_CURRENTS 0x2 2219 /* enum: Temperatures at locations around the PCB; DEBUG */ 2220 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 2221 /* enum: Set CPLD to idle */ 2222 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2223 /* enum: Read from CPLD register */ 2224 #define MC_CMD_AOE_OP_CPLD_READ 0x5 2225 /* enum: Write to CPLD register */ 2226 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2227 /* enum: Execute CPLD instruction */ 2228 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2229 /* enum: Reprogram the CPLD on the AOE device */ 2230 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 2231 /* enum: AOE power control */ 2232 #define MC_CMD_AOE_OP_POWER 0x9 2233 /* enum: AOE image loading */ 2234 #define MC_CMD_AOE_OP_LOAD 0xa 2235 /* enum: Fan monitoring */ 2236 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 2237 /* enum: Fan failures since last reset */ 2238 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 2239 /* enum: Get generic AOE MAC statistics */ 2240 #define MC_CMD_AOE_OP_MAC_STATS 0xd 2241 /* enum: Retrieve PHY specific information */ 2242 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 2243 /* enum: Write a number of JTAG primitive commands, return will give data */ 2244 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 2245 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 2246 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 2247 /* enum: Set the MTU offset between Siena and AOE MACs */ 2248 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 2249 /* enum: How link state is handled */ 2250 #define MC_CMD_AOE_OP_LINK_STATE 0x12 2251 /* enum: How Siena MAC statistics are reported (deprecated - use 2252 * MC_CMD_AOE_OP_ASIC_STATS) 2253 */ 2254 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 2255 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 2256 * command MC_CMD_AOE_OP_SIENA_STATS 2257 */ 2258 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 2259 /* enum: DDR memory information */ 2260 #define MC_CMD_AOE_OP_DDR 0x14 2261 /* enum: FC control */ 2262 #define MC_CMD_AOE_OP_FC 0x15 2263 /* enum: DDR ECC status reads */ 2264 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 2265 /* enum: Commands for MC-SPI Master emulation */ 2266 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 2267 /* enum: Commands for FC boot control */ 2268 #define MC_CMD_AOE_OP_FC_BOOT 0x18 2269 /* enum: Get number of internal ports */ 2270 #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 2271 /* enum: Get FC assert information and register dump */ 2272 #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a 2273 2274 /* MC_CMD_AOE_OUT msgresponse */ 2275 #define MC_CMD_AOE_OUT_LEN 0 2276 2277 /* MC_CMD_AOE_IN_INFO msgrequest */ 2278 #define MC_CMD_AOE_IN_INFO_LEN 4 2279 #define MC_CMD_AOE_IN_CMD_OFST 0 2280 #define MC_CMD_AOE_IN_CMD_LEN 4 2281 2282 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 2283 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 2284 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2285 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2286 2287 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 2288 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 2289 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2290 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2291 2292 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 2293 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 2294 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2295 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2296 2297 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 2298 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 2299 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2300 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2301 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 2302 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4 2303 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 2304 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4 2305 2306 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 2307 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 2308 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2309 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2310 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 2311 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4 2312 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 2313 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4 2314 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 2315 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4 2316 2317 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 2318 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 2319 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2320 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2321 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 2322 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4 2323 2324 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 2325 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 2326 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2327 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2328 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 2329 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4 2330 /* enum: Reprogram CPLD, poll for completion */ 2331 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 2332 /* enum: Reprogram CPLD, send event on completion */ 2333 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 2334 /* enum: Get status of reprogramming operation */ 2335 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 2336 2337 /* MC_CMD_AOE_IN_POWER msgrequest */ 2338 #define MC_CMD_AOE_IN_POWER_LEN 8 2339 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2340 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2341 /* Turn on or off AOE power */ 2342 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 2343 #define MC_CMD_AOE_IN_POWER_OP_LEN 4 2344 /* enum: Turn off FPGA power */ 2345 #define MC_CMD_AOE_IN_POWER_OFF 0x0 2346 /* enum: Turn on FPGA power */ 2347 #define MC_CMD_AOE_IN_POWER_ON 0x1 2348 /* enum: Clear peak power measurement */ 2349 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 2350 /* enum: Show current power in sensors output */ 2351 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 2352 /* enum: Show peak power in sensors output */ 2353 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 2354 /* enum: Show current DDR current */ 2355 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 2356 /* enum: Show peak DDR current */ 2357 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 2358 /* enum: Clear peak DDR current */ 2359 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 2360 2361 /* MC_CMD_AOE_IN_LOAD msgrequest */ 2362 #define MC_CMD_AOE_IN_LOAD_LEN 8 2363 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2364 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2365 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 2366 */ 2367 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 2368 #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4 2369 2370 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 2371 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 2372 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2373 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2374 /* If non zero report measured fan RPM rather than nominal */ 2375 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 2376 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4 2377 2378 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 2379 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 2380 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2381 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2382 2383 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 2384 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 2385 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2386 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2387 /* AOE port */ 2388 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 2389 #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4 2390 /* Host memory address for statistics */ 2391 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 2392 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 2393 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 2394 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 2395 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 2396 #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4 2397 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 2398 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 2399 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 2400 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 2401 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 2402 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 2403 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 2404 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 2405 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 2406 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 2407 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 2408 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 2409 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 2410 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 2411 /* Length of DMA data (optional) */ 2412 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 2413 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4 2414 2415 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 2416 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 2417 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2418 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2419 /* AOE port */ 2420 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 2421 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4 2422 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 2423 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4 2424 2425 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 2426 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 2427 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 2428 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 2429 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2430 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2431 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 2432 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4 2433 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 2434 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 2435 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 2436 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 2437 2438 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 2439 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 2440 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2441 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2442 /* Enable or disable access */ 2443 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 2444 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4 2445 /* enum: Enable access */ 2446 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 2447 /* enum: Disable access */ 2448 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 2449 2450 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 2451 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 2452 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2453 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2454 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 2455 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 2456 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4 2457 /* enum: Apply to all external ports */ 2458 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 2459 /* enum: Apply to all internal ports */ 2460 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 2461 /* The MTU offset to be applied to the external ports */ 2462 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 2463 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4 2464 2465 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 2466 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 2467 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2468 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2469 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 2470 #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4 2471 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 2472 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 2473 /* enum: AOE and associated external port */ 2474 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 2475 /* enum: AOE and OR of all external ports */ 2476 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 2477 /* enum: Individual ports */ 2478 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 2479 /* enum: Configure link state mode on given AOE port */ 2480 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 2481 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 2482 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 2483 /* enum: No-op */ 2484 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 2485 /* enum: logical OR of all SFP ports link status */ 2486 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 2487 /* enum: logical AND of all SFP ports link status */ 2488 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 2489 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 2490 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 2491 2492 /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */ 2493 #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4 2494 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2495 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2496 2497 /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */ 2498 #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4 2499 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2500 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2501 2502 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 2503 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 2504 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2505 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2506 /* How MAC statistics are reported */ 2507 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 2508 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 2509 /* enum: Statistics from Siena (default) */ 2510 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 2511 /* enum: Statistics from AOE external ports */ 2512 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 2513 2514 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 2515 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 2516 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2517 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2518 /* How MAC statistics are reported */ 2519 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 2520 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 2521 /* enum: Statistics from the ASIC (default) */ 2522 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 2523 /* enum: Statistics from AOE external ports */ 2524 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 2525 2526 /* MC_CMD_AOE_IN_DDR msgrequest */ 2527 #define MC_CMD_AOE_IN_DDR_LEN 12 2528 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2529 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2530 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 2531 #define MC_CMD_AOE_IN_DDR_BANK_LEN 4 2532 /* Enum values, see field(s): */ 2533 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2534 /* Page index of SPD data */ 2535 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 2536 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4 2537 2538 /* MC_CMD_AOE_IN_FC msgrequest */ 2539 #define MC_CMD_AOE_IN_FC_LEN 4 2540 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2541 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2542 2543 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 2544 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 2545 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2546 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2547 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 2548 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4 2549 /* Enum values, see field(s): */ 2550 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2551 2552 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 2553 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 2554 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2555 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2556 /* Basic commands for MC SPI Master emulation. */ 2557 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 2558 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4 2559 /* enum: MC SPI read */ 2560 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 2561 /* enum: MC SPI write */ 2562 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 2563 2564 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 2565 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 2566 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2567 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2568 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 2569 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4 2570 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 2571 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4 2572 2573 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 2574 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 2575 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2576 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2577 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 2578 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4 2579 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 2580 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4 2581 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 2582 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4 2583 2584 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 2585 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 2586 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2587 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2588 /* FC boot control flags */ 2589 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 2590 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4 2591 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 2592 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 2593 2594 /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ 2595 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 2596 /* Assertion status flag. */ 2597 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0 2598 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4 2599 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8 2600 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8 2601 /* enum: No crash data available */ 2602 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */ 2603 /* enum: New crash data available */ 2604 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */ 2605 /* enum: Crash data has been sent */ 2606 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */ 2607 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0 2608 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8 2609 /* enum: No crash has been recorded. */ 2610 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */ 2611 /* enum: Crash due to exception. */ 2612 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */ 2613 /* enum: Crash due to assertion. */ 2614 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */ 2615 /* Failing PC value */ 2616 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4 2617 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4 2618 /* Saved GP regs */ 2619 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8 2620 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4 2621 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31 2622 /* Exception Type */ 2623 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132 2624 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4 2625 /* Instruction at which exception occurred */ 2626 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136 2627 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4 2628 /* BAD Address that triggered address-based exception */ 2629 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2630 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4 2631 2632 /* MC_CMD_AOE_OUT_INFO msgresponse */ 2633 #define MC_CMD_AOE_OUT_INFO_LEN 44 2634 /* JTAG IDCODE of CPLD */ 2635 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 2636 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4 2637 /* Version of CPLD */ 2638 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 2639 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4 2640 /* JTAG IDCODE of FPGA */ 2641 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 2642 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4 2643 /* JTAG USERCODE of FPGA */ 2644 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 2645 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4 2646 /* FPGA type - read from CPLD straps */ 2647 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 2648 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 2649 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 2650 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 2651 /* FPGA state (debug) */ 2652 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 2653 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 2654 /* FPGA image - partition from which loaded */ 2655 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 2656 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4 2657 /* FC state */ 2658 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 2659 #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4 2660 /* enum: Set if watchdog working */ 2661 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 2662 /* enum: Set if MC-FC communications working */ 2663 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 2664 /* Random pieces of information */ 2665 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 2666 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 2667 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 2668 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 2669 /* enum: CPLD apparently good */ 2670 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 2671 /* enum: FPGA working normally */ 2672 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 2673 /* enum: FPGA is powered */ 2674 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 2675 /* enum: Board has incompatible SODIMMs fitted */ 2676 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 2677 /* enum: Board has ByteBlaster connected */ 2678 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 2679 /* enum: FPGA Boot flash has an invalid header. */ 2680 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 2681 /* enum: FPGA Application flash is accessible. */ 2682 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 2683 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 2684 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 2685 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 2686 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 2687 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 2688 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 2689 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 2690 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 2691 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 2692 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 2693 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 2694 /* enum: No error */ 2695 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 2696 /* enum: Bad address set in CPLD */ 2697 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 2698 /* enum: Bad header */ 2699 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 2700 /* enum: Bad text section details */ 2701 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 2702 /* enum: Bad checksum */ 2703 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 2704 /* enum: Bad BSP */ 2705 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 2706 /* enum: Flash mode is invalid */ 2707 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 2708 /* enum: FC application loaded and execution attempted */ 2709 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 2710 /* enum: FC application Started */ 2711 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 2712 /* enum: No bootrom in FPGA */ 2713 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 2714 2715 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 2716 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 2717 /* Set of currents and voltages (mA or mV as appropriate) */ 2718 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 2719 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 2720 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 2721 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 2722 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 2723 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 2724 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 2725 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 2726 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 2727 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 2728 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 2729 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 2730 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 2731 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 2732 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 2733 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 2734 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 2735 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 2736 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 2737 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 2738 2739 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 2740 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 2741 /* Set of temperatures */ 2742 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 2743 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 2744 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 2745 /* enum: The first set of enum values are for Modena code. */ 2746 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 2747 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 2748 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 2749 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 2750 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 2751 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 2752 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 2753 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 2754 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 2755 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 2756 /* enum: The second set of enum values are for Sorrento code. */ 2757 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 2758 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 2759 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 2760 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 2761 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 2762 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 2763 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 2764 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 2765 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 2766 2767 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 2768 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 2769 /* The value read from the CPLD */ 2770 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 2771 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4 2772 2773 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 2774 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 2775 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 2776 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 2777 /* Failure counts for each fan */ 2778 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 2779 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 2780 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 2781 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 2782 2783 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 2784 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 2785 /* Results of status command (only) */ 2786 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 2787 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4 2788 2789 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 2790 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 2791 2792 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 2793 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 2794 2795 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 2796 #define MC_CMD_AOE_OUT_LOAD_LEN 0 2797 2798 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 2799 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 2800 2801 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 2802 * for details 2803 */ 2804 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 2805 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 2806 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 2807 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 2808 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 2809 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 2810 2811 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 2812 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 2813 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 2814 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 2815 /* in bytes */ 2816 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 2817 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 2818 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 2819 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 2820 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 2821 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 2822 2823 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 2824 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 2825 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 2826 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 2827 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 2828 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 2829 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 2830 /* out bytes */ 2831 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 2832 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4 2833 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 2834 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 2835 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 2836 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 2837 2838 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 2839 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 2840 2841 /* MC_CMD_AOE_OUT_DDR msgresponse */ 2842 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 2843 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 2844 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 2845 /* Information on the module. */ 2846 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 2847 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 2848 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 2849 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 2850 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 2851 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 2852 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 2853 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 2854 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 2855 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 2856 /* Memory size, in MB. */ 2857 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 2858 #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4 2859 /* The memory type, as reported from SPD information */ 2860 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 2861 #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4 2862 /* Nominal voltage of the module (as applied) */ 2863 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 2864 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4 2865 /* SPD data read from the module */ 2866 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 2867 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 2868 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 2869 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 2870 2871 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 2872 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 2873 2874 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 2875 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 2876 2877 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 2878 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 2879 2880 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 2881 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 2882 2883 /* MC_CMD_AOE_OUT_FC msgresponse */ 2884 #define MC_CMD_AOE_OUT_FC_LEN 0 2885 2886 /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */ 2887 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4 2888 /* get the number of internal ports */ 2889 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0 2890 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4 2891 2892 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 2893 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 2894 /* Flags describing status info on the module. */ 2895 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 2896 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4 2897 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 2898 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 2899 /* DDR ECC status on the module. */ 2900 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 2901 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4 2902 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 2903 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 2904 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 2905 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 2906 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 2907 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 2908 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 2909 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 2910 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 2911 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 2912 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 2913 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 2914 2915 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 2916 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 2917 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 2918 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4 2919 2920 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 2921 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 2922 2923 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 2924 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 2925 2926 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 2927 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 2928 2929 #endif /* _SYS_EFX_REGS_MCDI_AOE_H */ 2930