1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 #ifndef _UMCS7840_H_ 29 #define _UMCS7840_H_ 30 31 #define UMCS7840_MAX_PORTS 4 32 33 #define UMCS7840_READ_LENGTH 1 /* bytes */ 34 #define UMCS7840_CTRL_TIMEOUT 500 /* ms */ 35 36 /* Read/Wrtire registers vendor commands */ 37 #define MCS7840_RDREQ 0x0d 38 #define MCS7840_WRREQ 0x0e 39 40 /* Read/Wrtie EEPROM values */ 41 #define MCS7840_EEPROM_RW_WVALUE 0x0900 42 43 /* 44 * All these registers are documented only in full datasheet, 45 * which can be requested from MosChip tech support. 46 */ 47 #define MCS7840_DEV_REG_SP1 0x00 /* Options for UART 1, R/W */ 48 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1, 49 * R/W */ 50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong 51 * register, R/W */ 52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong 53 * register, R/W */ 54 /* DCRx_1 Registers goes here (see below, they are documented) */ 55 #define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits, 56 * undocumented, see notes 57 * below R/W */ 58 #define MCS7840_DEV_REG_SP2 0x08 /* Options for UART 2, R/W */ 59 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2, 60 * R/W */ 61 #define MCS7840_DEV_REG_SP3 0x0a /* Options for UART 3, R/W */ 62 #define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3, 63 * R/W */ 64 #define MCS7840_DEV_REG_SP4 0x0c /* Options for UART 4, R/W */ 65 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4, 66 * R/W */ 67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ 68 #define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */ 69 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ 70 #define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt 71 * endpoint control, R/W */ 72 #define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */ 73 #define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 & 74 * 2, R/W */ 75 #define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 & 76 * 4, R/W */ 77 #define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */ 78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ 79 #define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */ 80 #define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */ 81 #define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */ 82 #define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */ 83 #define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */ 84 #define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */ 85 #define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */ 86 #define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */ 87 #define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */ 88 #define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */ 89 #define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */ 90 #define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */ 91 #define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration, 92 * R/Only */ 93 #define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap 94 * configuration for Port 1, 95 * R/W */ 96 #define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap 97 * configuration for Port 2, 98 * R/W */ 99 #define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap 100 * configuration for Port 3, 101 * R/W */ 102 #define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap 103 * configuration for Port 4, 104 * R/W */ 105 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 & 106 * 2, R/W */ 107 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 & 108 * 4, R/W */ 109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port 110 * 1, contains number of 111 * available bytes, R/Only */ 112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port 113 * 1, contains number of 114 * available bytes, R/Only */ 115 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port 116 * 2, contains number of 117 * available bytes, R/Only */ 118 #define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port 119 * 2, contains number of 120 * available bytes, R/Only */ 121 #define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port 122 * 3, contains number of 123 * available bytes, R/Only */ 124 #define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port 125 * 3, contains number of 126 * available bytes, R/Only */ 127 #define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port 128 * 4, contains number of 129 * available bytes, R/Only */ 130 #define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port 131 * 4, contains number of 132 * available bytes, R/Only */ 133 #define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out 134 * frames for Port 1, R/W */ 135 #define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out 136 * frames for Port 1, R/W */ 137 #define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out 138 * frames for Port 1, R/W */ 139 #define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out 140 * frames for Port 1, R/W */ 141 #define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out 142 * frames, R/W */ 143 #define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshold 144 * value for Bulk-Out for Port 145 * 1, R/W */ 146 #define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshold 147 * value for Bulk-Out and 148 * enable flag for Port 1, R/W */ 149 #define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshold 150 * value for Bulk-Out for Port 151 * 2, R/W */ 152 #define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshold 153 * value for Bulk-Out and 154 * enable flag for Port 2, R/W */ 155 #define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshold 156 * value for Bulk-Out for Port 157 * 3, R/W */ 158 #define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshold 159 * value for Bulk-Out and 160 * enable flag for Port 3, R/W */ 161 #define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshold 162 * value for Bulk-Out for Port 163 * 4, R/W */ 164 #define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshold 165 * value for Bulk-Out and 166 * enable flag for Port 4, R/W */ 167 168 /* Bits for SPx registers */ 169 #define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the 170 * Bulk-In FIFO, default = 0 */ 171 #define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART, 172 * which were received with 173 * errors, default = 0 */ 174 #define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */ 175 #define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */ 176 #define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK 177 * source */ 178 #define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed 179 * = 115200 bps, default */ 180 #define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed 181 * = 230400 bps */ 182 #define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed 183 * = 403200 bps */ 184 #define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed 185 * = 460800 bps */ 186 #define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed 187 * = 806400 bps */ 188 #define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed 189 * = 921600 bps */ 190 #define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed 191 * = 1.5 Mbps */ 192 #define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed 193 * = 3.0 Mbps */ 194 #define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted 195 * to get clock value */ 196 #define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */ 197 198 /* Bits for CONTROLx registers */ 199 #define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow 200 * control (when power 201 * down? It is unclear 202 * in documents), 203 * default = 0 */ 204 #define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */ 205 #define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are 206 * translated to MSR, 207 * default = 0 */ 208 #define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports 209 * 2,3,4 */ 210 #define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is 211 * finished, USB 212 * enumeration memory 213 * can be used as FIFOs */ 214 #define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input, 215 * works for IrDA mode 216 * only, default = 0 */ 217 #define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic, 218 * works only for 219 * RS-232/RS-485 mode, 220 * default = 0 */ 221 #define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when 222 * TX is in progress, 223 * works for IrDA mode 224 * only, default = 0 */ 225 #define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */ 226 227 /* 228 * Bits for PINPONGx registers 229 * These registers control how often two input buffers 230 * for Bulk-In FIFOs are swapped. One of buffers is used 231 * for USB trnasfer, other for receiving data from UART. 232 * Exact meaning of 15 bit value in these registers is unknown 233 */ 234 #define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW 235 * register */ 236 #define MCS7840_DEV_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW 237 * register */ 238 239 /* 240 * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support 241 * confirms, that it is register for GPIO_0 and GPIO_1 data input/output. 242 * Chips has 2 GPIO, but first one (lower bit) MUST be used by device 243 * authors as "number of port" indicator, grounded (0) for two-port 244 * devices and pulled-up to 1 for 4-port devices. 245 */ 246 #define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports 247 * configured */ 248 #define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */ 249 #define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */ 250 251 /* 252 * Constants for PLL dividers 253 * Ouptut frequency of PLL is: 254 * Fout = (N/M) * Fin. 255 * Default PLL input frequency Fin is 12Mhz (on-chip). 256 */ 257 #define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M 258 * divider */ 259 #define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */ 260 #define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is 261 * forbidden */ 262 #define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */ 263 #define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */ 264 #define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N 265 * divider */ 266 #define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */ 267 #define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is 268 * forbidden */ 269 #define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */ 270 #define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */ 271 272 /* Bits for CLOCK_MUX register */ 273 #define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock 274 * input */ 275 #define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */ 276 #define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended) 277 * PLL input */ 278 #define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */ 279 #define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */ 280 #define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is 281 * 20MHz-100MHz (default), 1 = 282 * 100MHz-300MHz range */ 283 #define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes 284 * fro Interrupt USB pipe with 285 * USB FIFOs statuses, default 286 * = 0 */ 287 #define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */ 288 #define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */ 289 #define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */ 290 #define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */ 291 292 /* Bits for CLOCK_SELECTxx registers */ 293 #define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in 294 * CLOCK_SELECT12 */ 295 #define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in 296 * CLOCK_SELECT12 */ 297 #define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in 298 * CLOCK_SELECT12 */ 299 #define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in 300 * CLOCK_SELECT12 */ 301 #define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in 302 * CLOCK_SELECT23 */ 303 #define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in 304 * CLOCK_SELECT23 */ 305 #define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in 306 * CLOCK_SELECT23 */ 307 #define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in 308 * CLOCK_SELECT23 */ 309 #define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived 310 * from 96Mhz, default for all 311 * ports */ 312 #define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */ 313 #define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */ 314 #define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */ 315 #define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N 316 * dividers) */ 317 #define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input 318 * (device-dependend) */ 319 #define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */ 320 #define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */ 321 322 /* Bits for MODE register */ 323 #define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */ 324 #define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High 325 * (default), 1: Reserved (?) */ 326 #define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use 327 * hardocded values (default) 328 * (?) */ 329 #define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed, 330 * default = 0 */ 331 #define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is 332 * bypassed, default = 0 */ 333 #define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA 334 * active, 1: 2 Serial Ports / 335 * IrDA active */ 336 #define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled, 337 * default */ 338 #define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated 339 * (could be turned on), 340 * default */ 341 342 /* Bits for SPx ICG */ 343 #define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as 344 * number of BAUD clocks of 345 * pause */ 346 347 /* 348 * Bits for RX_SAMPLINGxx registers 349 * These registers control when bit value will be sampled within 350 * the baud period. 351 * 0 is very beginning of period, 15 is very end, 7 is the middle. 352 */ 353 #define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in 354 * RX_SAMPLING12 */ 355 #define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in 356 * RX_SAMPLING12 */ 357 #define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in 358 * RX_SAMPLING12 */ 359 #define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in 360 * RX_SAMPLING12 */ 361 #define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in 362 * RX_SAMPLING23 */ 363 #define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in 364 * RX_SAMPLING23 */ 365 #define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in 366 * RX_SAMPLING23 */ 367 #define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in 368 * RX_SAMPLING23 */ 369 #define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */ 370 #define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX 371 * Sampling, center of period */ 372 #define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */ 373 374 /* Bits for ZERO_PERIODx */ 375 #define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests 376 * befor sending zero-sized 377 * reply */ 378 379 /* Bits for ZERO_ENABLE */ 380 #define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending 381 * zero-sized replies for port 382 * 1, default */ 383 #define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending 384 * zero-sized replies for port 385 * 2, default */ 386 #define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending 387 * zero-sized replies for port 388 * 3, default */ 389 #define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending 390 * zero-sized replies for port 391 * 4, default */ 392 393 /* Bits for THR_VAL_HIGHx */ 394 #define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */ 395 #define MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */ 396 #define MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */ 397 #define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */ 398 399 /* These are documented in "public" datasheet */ 400 #define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port 401 * 1, R/W */ 402 #define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port 403 * 1, R/W */ 404 #define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port 405 * 1, R/W */ 406 #define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port 407 * 2, R/W */ 408 #define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port 409 * 2, R/W */ 410 #define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port 411 * 2, R/W */ 412 #define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port 413 * 3, R/W */ 414 #define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port 415 * 3, R/W */ 416 #define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port 417 * 3, R/W */ 418 #define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port 419 * 4, R/W */ 420 #define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port 421 * 4, R/W */ 422 #define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port 423 * 4, R/W */ 424 425 /* Bits of DCR0 registers, documented in datasheet */ 426 #define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver 427 * when USB Suspend is 428 * engaged, default = 1 */ 429 #define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */ 430 #define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS 431 * ONLY FOR PORT 1 */ 432 #define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input 433 * (0b00), WORKS ONLY 434 * FOR PORT 1 */ 435 #define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input 436 * (0b10), WORKS ONLY 437 * FOR PORT 1 */ 438 #define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH, 439 * default = 0 (low) */ 440 #define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by 441 * state of TX buffer, 442 * default = 0 443 * (controlled by MCR) */ 444 #define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */ 445 #define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */ 446 447 /* Bits of DCR1 registers, documented in datasheet */ 448 #define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO 449 * current value, WORKS 450 * ONLY FOR PORT 1 */ 451 #define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current 452 * 6mA, WORKS ONLY FOR 453 * PORT 1 */ 454 #define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current 455 * 8mA, defauilt, WORKS 456 * ONLY FOR PORT 1 */ 457 #define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current 458 * 10mA, WORKS ONLY FOR 459 * PORT 1 */ 460 #define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current 461 * 12mA, WORKS ONLY FOR 462 * PORT 1 */ 463 #define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART 464 * signals current value */ 465 #define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current 466 * 6mA */ 467 #define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current 468 * 8mA, defauilt */ 469 #define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current 470 * 10mA */ 471 #define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current 472 * 12mA */ 473 #define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB 474 * Wakeup */ 475 #define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power 476 * down when not needed, 477 * WORKS ONLY FOR PORT 1 */ 478 #define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of 479 * interrupt data, with 480 * FIFO statistics, 481 * WORKS ONLY FOR PORT 1 */ 482 #define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */ 483 484 /* 485 * Bits of DCR2 registers, documented in datasheet 486 * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and 487 * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled). 488 */ 489 #define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change, 490 * default = 0 */ 491 #define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change, 492 * default = 0 */ 493 #define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change, 494 * default = 1 */ 495 #define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change, 496 * default = 0 */ 497 #define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change, 498 * default = 0 */ 499 #define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME 500 * signal, DISCONNECT 501 * otherwise, default = 1 */ 502 #define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */ 503 #define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1: 504 * Pin 12 Active High, default 505 * = 0 */ 506 507 /* Interrupt endpoint bytes & bits */ 508 #define MCS7840_IEP_FIFO_STATUS_INDEX 5 509 /* 510 * Thesse can be calculated as "1 << portnumber" for Bulk-out and 511 * "1 << (portnumber+1)" for Bulk-in 512 */ 513 #define MCS7840_IEP_BO_PORT1_HASDATA 0x01 514 #define MCS7840_IEP_BI_PORT1_HASDATA 0x02 515 #define MCS7840_IEP_BO_PORT2_HASDATA 0x04 516 #define MCS7840_IEP_BI_PORT2_HASDATA 0x08 517 #define MCS7840_IEP_BO_PORT3_HASDATA 0x10 518 #define MCS7840_IEP_BI_PORT3_HASDATA 0x20 519 #define MCS7840_IEP_BO_PORT4_HASDATA 0x40 520 #define MCS7840_IEP_BI_PORT4_HASDATA 0x80 521 522 /* Documented UART registers (fully compatible with 16550 UART) */ 523 #define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding 524 * Register W/Only */ 525 #define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register 526 * R/Only */ 527 #define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register - 528 * R/W */ 529 #define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register - 530 * W/Only */ 531 #define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter 532 * R/Only */ 533 #define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */ 534 #define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */ 535 #define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */ 536 #define MCS7840_UART_REG_MSR 0x06 /* Modem status register 537 * R/Only */ 538 #define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */ 539 540 #define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */ 541 #define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */ 542 543 /* IER bits */ 544 #define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */ 545 #define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */ 546 #define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */ 547 #define MCS7840_UART_IER_MODEM 0x08 /* Modem status change 548 * interrumpt mask */ 549 #define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */ 550 551 /* FCR bits */ 552 #define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */ 553 #define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */ 554 #define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */ 555 #define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR 556 * Interrupt Trigger level */ 557 #define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */ 558 #define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */ 559 #define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */ 560 #define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */ 561 562 /* ISR bits */ 563 #define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */ 564 #define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt 565 * source */ 566 #define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */ 567 #define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */ 568 #define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */ 569 #define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */ 570 #define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */ 571 572 /* LCR bits */ 573 #define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */ 574 #define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */ 575 #define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */ 576 #define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */ 577 #define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */ 578 579 #define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */ 580 #define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */ 581 #define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on 582 * data length */ 583 584 #define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */ 585 #define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */ 586 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ 587 #define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */ 588 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ 589 #define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */ 590 591 #define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */ 592 #define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of 593 * xHR/IER */ 594 595 /* LSR bits */ 596 #define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */ 597 #define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */ 598 #define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */ 599 #define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */ 600 #define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK signal received */ 601 #define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty, 602 * ready for transmit */ 603 #define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */ 604 605 /* MCR bits */ 606 #define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active 607 * (low) */ 608 #define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active 609 * (low) */ 610 #define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from 611 * code, not documented) */ 612 #define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test 613 * mode */ 614 #define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control 615 * in 550 (FIFO) mode */ 616 #define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control 617 * in 550 (FIFO) mode */ 618 #define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in 619 * 550 (FIFO) mode */ 620 621 /* MSR bits */ 622 #define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last 623 * read */ 624 #define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last 625 * read */ 626 #define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to 627 * high since last read */ 628 #define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last 629 * read */ 630 #define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */ 631 #define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */ 632 #define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */ 633 #define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */ 634 635 /* SCRATCHPAD bits */ 636 #define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */ 637 #define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High 638 * = RX */ 639 #define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High 640 * = TX */ 641 642 #define MCS7840_CONFIG_INDEX 0 643 #define MCS7840_IFACE_INDEX 0 644 645 #endif 646