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Searched refs:MCPhysReg (Results 1 – 25 of 220) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.h256 using llvm::MCPhysReg;
259 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
260 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
261 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
262 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \
263 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
264 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
265 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
266 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
267 static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
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/freebsd/contrib/llvm-project/llvm/lib/DWARFCFIChecker/
H A DRegisters.h27 inline bool isSuperReg(const MCRegisterInfo *MCRI, MCPhysReg Reg) { in isSuperReg()
31 inline SmallVector<MCPhysReg> getSuperRegs(const MCRegisterInfo *MCRI) { in getSuperRegs()
32 SmallVector<MCPhysReg> SuperRegs; in getSuperRegs()
35 MCPhysReg Reg = RegClass.getRegister(I); in getSuperRegs()
45 inline SmallVector<MCPhysReg> getTrackingRegs(const MCRegisterInfo *MCRI) { in getTrackingRegs()
46 SmallVector<MCPhysReg> TrackingRegs; in getTrackingRegs()
53 inline MCPhysReg getSuperReg(const MCRegisterInfo *MCRI, MCPhysReg Reg) { in getSuperReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVCallingConv.cpp46 static const MCPhysReg ArgFPR16s[] = {RISCV::F10_H, RISCV::F11_H, RISCV::F12_H,
49 static const MCPhysReg ArgFPR32s[] = {RISCV::F10_F, RISCV::F11_F, RISCV::F12_F,
52 static const MCPhysReg ArgFPR64s[] = {RISCV::F10_D, RISCV::F11_D, RISCV::F12_D,
56 static const MCPhysReg ArgVRs[] = {
60 static const MCPhysReg ArgVRM2s[] = {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2,
63 static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
65 static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8};
66 static const MCPhysReg ArgVRN2M1s[] = {
71 static const MCPhysReg ArgVRN3M1s[] = {
77 static const MCPhysReg ArgVRN4M1s[] = {
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h38 using iterator = const MCPhysReg*;
39 using const_iterator = const MCPhysReg*;
171 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
194 mutable std::vector<std::vector<MCPhysReg>> RegAliasesCache;
195 ArrayRef<MCPhysReg> getCachedAliasesOf(MCRegister R) const;
258 detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>,
281 const MCPhysReg (*RURoots)[2], unsigned NRU, in InitMCRegisterInfo()
524 std::forward_iterator_tag, const MCPhysReg> {
526 MCPhysReg Val;
537 Val = MCPhysReg(*I);
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/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp27 static std::function<bool(MCPhysReg)>
29 return [&MRI](MCPhysReg R) { return !MRI.isArtificial(R); }; in isNonArtificial()
63 MCPhysReg WriteRef::getRegisterID() const { in getRegisterID()
116 MCPhysReg RegID = WS.getRegisterID(); in onInstructionExecuted()
127 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; in onInstructionExecuted()
135 for (MCPhysReg I : MRI.subregs(RegID)) { in onInstructionExecuted()
144 for (MCPhysReg I : MRI.superregs(RegID)) { in onInstructionExecuted()
175 for (const MCPhysReg Reg : RC) { in addRegisterFile()
190 for (MCPhysReg I : MRI.subregs(Reg)) { in addRegisterFile()
236 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h148 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
151 MCPhysReg PReg;
317 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
324 void DeallocateReg(MCPhysReg Reg) { in DeallocateReg()
332 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
340 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
351 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
357 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
365 ArrayRef<MCPhysReg> AllocateRegBlock(ArrayRef<MCPhysReg> Regs, in AllocateRegBlock()
393 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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H A DRegisterClassInfo.h37 std::unique_ptr<MCPhysReg[]> Order;
41 operator ArrayRef<MCPhysReg>() const {
60 SmallVector<MCPhysReg, 16> LastCalleeSavedRegs;
63 SmallVector<MCPhysReg> CalleeSavedAliases;
106 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
H A DLivePhysRegs.h54 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
86 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg()
101 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
132 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp23 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
64 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
65 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
66 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
67 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
115 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
116 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
152 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
154 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
158 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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H A DARMBaseRegisterInfo.h45 const MCPhysReg *CSRegs) { in isCalleeSavedRegister()
64 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
65 const MCPhysReg *
84 ArrayRef<MCPhysReg>
106 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
107 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.h31 const SmallVector<MCPhysReg, 16> Hints;
32 ArrayRef<MCPhysReg> Order;
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
117 static_cast<uint32_t>(std::numeric_limits<MCPhysReg>::max())); in isHint()
H A DRegisterClassInfo.cpp59 const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); in runOnMachineFunction()
86 for (const MCPhysReg *I = CSR; *I; ++I) { in runOnMachineFunction()
98 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
137 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
140 SmallVector<MCPhysReg, 16> CSRAlias; in compute()
147 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF, Reverse); in compute()
148 std::vector<MCPhysReg> ReverseOrder; in compute()
151 RawOrder = ArrayRef<MCPhysReg>(ReverseOrder); in compute()
H A DAllocationOrder.cpp35 SmallVector<MCPhysReg, 16> Hints; in create()
42 for (MCPhysReg Hint : Hints) in create()
48 [&](MCPhysReg Hint) { return is_contained(Order, Hint); }) && in create()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.cpp13 const MCPhysReg SystemZ::ELFArgGPRs[SystemZ::ELFNumArgGPRs] = {
17 const MCPhysReg SystemZ::ELFArgFPRs[SystemZ::ELFNumArgFPRs] = {
22 const MCPhysReg SystemZ::XPLINK64ArgGPRs[SystemZ::XPLINK64NumArgGPRs] = {
27 const MCPhysReg SystemZ::XPLINK64ArgFPRs[SystemZ::XPLINK64NumArgFPRs] = {
H A DSystemZRegisterInfo.h62 virtual const MCPhysReg *
94 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const final;
117 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const final;
149 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
150 SmallVectorImpl<MCPhysReg> &Hints,
161 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h42 MCPhysReg RegisterID;
59 MCPhysReg getRegisterID() const;
167 MCPhysReg RenameAs;
168 MCPhysReg AliasRegID;
240 MCPhysReg RegisterID = 0;
290 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp33 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_PPC64_ELF_Shadow_GPR_Regs()
71 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs()
96 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
121 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
149 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
150 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
178 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
179 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp22 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
25 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
28 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
31 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
34 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
37 static const MCPhysReg ZRegList[] = {AArch64::Z0, AArch64::Z1, AArch64::Z2,
40 static const MCPhysReg PRegList[] = {AArch64::P0, AArch64::P1, AArch64::P2,
142 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block()
179 ArrayRef<MCPhysReg> RegResult = State.AllocateRegBlock( in CC_AArch64_Custom_Block()
H A DAArch64RedundantCopyElimination.cpp84 MCPhysReg Reg;
86 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {} in RegImm()
181 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
182 MCPhysReg SrcReg = PredI.getOperand(1).getReg(); in knownRegValInBlock()
247 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
319 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock()
320 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg(); in optimizeBlock()
400 MCPhysReg CmpReg = KnownReg.Reg; in optimizeBlock()
454 for (MCPhysReg KnownReg : UsedKnownRegs) in optimizeBlock()
H A DAArch64RegisterInfo.h48 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
49 const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
50 const MCPhysReg *
139 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
140 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
67 static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) { in CC_X86_VectorCallGetSSEs()
69 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2, in CC_X86_VectorCallGetSSEs()
75 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2, in CC_X86_VectorCallGetSSEs()
80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
85 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() { in CC_X86_64_VectorCallGetGPRs()
86 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
360 static const MCPhysReg Regs[] = {X86::RDI, X86::RSI, X86::RDX, in CC_X86_64_I128()
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H A DX86RegisterInfo.h99 const MCPhysReg *
103 const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;
104 const MCPhysReg *
174 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
175 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp92 const MCPhysReg *
151 static const MCPhysReg ReservedGPR32[] = { in getReservedRegs()
155 static const MCPhysReg ReservedGPR64[] = { in getReservedRegs()
162 for (MCPhysReg R : ReservedGPR32) in getReservedRegs()
172 for (MCPhysReg R : ReservedGPR64) in getReservedRegs()
183 for (MCPhysReg Reg : Mips::AFGR64RegClass) in getReservedRegs()
187 for (MCPhysReg Reg : Mips::FGR64RegClass) in getReservedRegs()
220 for (MCPhysReg Reg : Mips::MSACtrlRegClass) in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h145 MCPhysReg RegisterID;
173 MCPhysReg RegisterID;
188 MCPhysReg RegID;
209 MCPhysReg RegisterID;
249 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
261 MCPhysReg getRegisterID() const { return RegisterID; } in getRegisterID()
262 void setRegisterID(const MCPhysReg RegID) { RegisterID = RegID; } in setRegisterID()
304 LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
330 MCPhysReg RegisterID;
357 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) in ReadState()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp61 const MCPhysReg *
66 static const MCPhysReg Int32[] = { in getCallerSavedRegs()
69 static const MCPhysReg Int64[] = { in getCallerSavedRegs()
72 static const MCPhysReg Pred[] = { in getCallerSavedRegs()
75 static const MCPhysReg VecSgl[] = { in getCallerSavedRegs()
80 static const MCPhysReg VecDbl[] = { in getCallerSavedRegs()
83 static const MCPhysReg VecPred[] = { in getCallerSavedRegs()
104 static const MCPhysReg Empty[] = { 0 }; in getCallerSavedRegs()
113 const MCPhysReg *
115 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
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