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Searched refs:MCPhysReg (Results 1 – 25 of 214) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.h254 using llvm::MCPhysReg;
257 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
258 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
259 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
260 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \
261 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
262 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
263 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
264 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
265 static const MCPhysReg RRegsNoR
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h37 using iterator = const MCPhysReg*;
38 using const_iterator = const MCPhysReg*;
167 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
190 mutable std::vector<std::vector<MCPhysReg>> RegAliasesCache;
191 ArrayRef<MCPhysReg> getCachedAliasesOf(MCPhysReg R) const;
254 detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>,
275 const MCPhysReg (*RURoots)[2], unsigned NRU, in InitMCRegisterInfo()
508 std::forward_iterator_tag, const MCPhysReg> {
510 MCPhysReg Val;
521 Val = MCPhysReg(*I);
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h147 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
150 MCPhysReg PReg;
315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
322 void DeallocateReg(MCPhysReg Reg) { in DeallocateReg()
330 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
338 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
355 MCPhysReg Re in AllocateReg()
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H A DLivePhysRegs.h54 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
83 void addReg(MCPhysReg Reg) { in addReg()
86 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg()
92 void removeReg(MCPhysReg Reg) { in removeReg()
101 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
109 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); } in contains()
112 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
132 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
H A DRegisterClassInfo.h36 std::unique_ptr<MCPhysReg[]> Order;
40 operator ArrayRef<MCPhysReg>() const {
57 SmallVector<MCPhysReg, 16> LastCalleeSavedRegs;
60 SmallVector<MCPhysReg> CalleeSavedAliases;
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp58 MCPhysReg WriteRef::getRegisterID() const { in getRegisterID()
111 MCPhysReg RegID = WS.getRegisterID(); in onInstructionExecuted()
122 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; in onInstructionExecuted()
130 for (MCPhysReg I : MRI.subregs(RegID)) { in onInstructionExecuted()
139 for (MCPhysReg I : MRI.superregs(RegID)) { in onInstructionExecuted()
170 for (const MCPhysReg Reg : RC) { in addRegisterFile()
185 for (MCPhysReg I : MRI.subregs(Reg)) { in addRegisterFile()
231 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite()
282 MCPhysReg ZeroRegisterID = in addRegisterWrite()
285 for (MCPhysReg I : MRI.subregs(ZeroRegisterID)) in addRegisterWrite()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocFast.cpp203 MCPhysReg PhysReg = 0; ///< Currently held here.
221 DenseMap<Register, MCPhysReg> BundleVirtRegsMap;
279 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
280 bool isPhysRegFree(MCPhysReg PhysReg) const;
283 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
289 bool isClobberedByRegMasks(MCPhysReg PhysReg) const { in isClobberedByRegMasks()
296 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr()
307 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr()
315 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr()
344 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
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H A DAllocationOrder.h31 const SmallVector<MCPhysReg, 16> Hints;
32 ArrayRef<MCPhysReg> Order;
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
117 static_cast<uint32_t>(std::numeric_limits<MCPhysReg>::max())); in isHint()
H A DLivePhysRegs.cpp32 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers) { in removeRegsInMask() argument
81 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers) { in stepForward() argument
130 for (MCPhysReg R : *this) in print()
142 MCPhysReg Reg) const { in available()
157 MCPhysReg Reg = LI.PhysReg; in addBlockLiveIns()
177 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) in addCalleeSavedRegs()
205 for (MCPhysReg R : Pristine) in addPristines()
264 for (MCPhysReg Reg : LiveRegs) { in addLiveIns()
268 if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) { in addLiveIns()
H A DRegisterClassInfo.cpp57 const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); in runOnMachineFunction()
84 for (const MCPhysReg *I = CSR; *I; ++I) { in runOnMachineFunction()
96 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
134 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
137 SmallVector<MCPhysReg, 16> CSRAlias; in compute()
144 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
H A DAllocationOrder.cpp35 SmallVector<MCPhysReg, 16> Hints; in create()
42 for (MCPhysReg Hint : Hints) in create()
48 [&](MCPhysReg Hint) { return is_contained(Order, Hint); }) && in create()
H A DLiveVariables.cpp224 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastPartialDef()
245 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) in FindLastPartialDef()
275 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegUse()
286 for (MCPhysReg SS : TRI->subregs(SubReg)) in HandlePhysRegUse()
297 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in HandlePhysRegUse()
312 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastRefOrPartRef()
360 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegKill()
373 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg)) in HandlePhysRegKill()
389 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegKill()
409 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg)) in HandlePhysRegKill()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
116 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
159 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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H A DARMBaseRegisterInfo.h120 const MCPhysReg *CSRegs) { in isCalleeSavedRegister()
139 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
140 const MCPhysReg *
159 ArrayRef<MCPhysReg>
181 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
182 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.cpp14 const MCPhysReg SystemZ::ELFArgGPRs[SystemZ::ELFNumArgGPRs] = {
18 const MCPhysReg SystemZ::ELFArgFPRs[SystemZ::ELFNumArgFPRs] = {
23 const MCPhysReg SystemZ::XPLINK64ArgGPRs[SystemZ::XPLINK64NumArgGPRs] = {
28 const MCPhysReg SystemZ::XPLINK64ArgFPRs[SystemZ::XPLINK64NumArgFPRs] = {
H A DSystemZRegisterInfo.h62 virtual const MCPhysReg *
94 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const final;
117 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const final;
149 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
150 SmallVectorImpl<MCPhysReg> &Hints,
161 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h42 MCPhysReg RegisterID;
59 MCPhysReg getRegisterID() const;
167 MCPhysReg RenameAs;
168 MCPhysReg AliasRegID;
240 MCPhysReg RegisterID = 0;
290 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp34 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_PPC64_ELF_Shadow_GPR_Regs()
72 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs()
97 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
122 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
150 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
151 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
179 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
180 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp34 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
68 static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) { in CC_X86_VectorCallGetSSEs()
70 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2, in CC_X86_VectorCallGetSSEs()
76 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2, in CC_X86_VectorCallGetSSEs()
81 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
86 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() { in CC_X86_64_VectorCallGetGPRs()
87 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
97 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister()
243 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
H A DX86RegisterInfo.h103 const MCPhysReg *
105 const MCPhysReg *
175 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
176 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp92 const MCPhysReg *
151 static const MCPhysReg ReservedGPR32[] = { in getReservedRegs()
155 static const MCPhysReg ReservedGPR64[] = { in getReservedRegs()
162 for (MCPhysReg R : ReservedGPR32) in getReservedRegs()
172 for (MCPhysReg R : ReservedGPR64) in getReservedRegs()
183 for (MCPhysReg Reg : Mips::AFGR64RegClass) in getReservedRegs()
187 for (MCPhysReg Reg : Mips::FGR64RegClass) in getReservedRegs()
219 for (MCPhysReg Reg : Mips::MSACtrlRegClass) in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
38 static const MCPhysReg ZRegList[] = {AArch64::Z0, AArch64::Z1, AArch64::Z2,
41 static const MCPhysReg PRegList[] = {AArch64::P0, AArch64::P1, AArch64::P2,
143 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block()
H A DAArch64RedundantCopyElimination.cpp87 MCPhysReg Reg;
89 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {} in RegImm()
185 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
186 MCPhysReg SrcReg = PredI.getOperand(1).getReg(); in knownRegValInBlock()
251 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
323 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock()
324 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg(); in optimizeBlock()
404 MCPhysReg CmpReg = KnownReg.Reg; in optimizeBlock()
458 for (MCPhysReg KnownReg : UsedKnownRegs) in optimizeBlock()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h144 MCPhysReg RegisterID;
172 MCPhysReg RegisterID;
187 MCPhysReg RegID;
208 MCPhysReg RegisterID;
248 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
260 MCPhysReg getRegisterID() const { return RegisterID; } in getRegisterID()
261 void setRegisterID(const MCPhysReg RegID) { RegisterID = RegID; } in setRegisterID()
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
329 MCPhysReg RegisterID;
356 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) in ReadState()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp66 const MCPhysReg *
71 static const MCPhysReg Int32[] = { in getCallerSavedRegs()
74 static const MCPhysReg Int64[] = { in getCallerSavedRegs()
77 static const MCPhysReg Pred[] = { in getCallerSavedRegs()
80 static const MCPhysReg VecSgl[] = { in getCallerSavedRegs()
85 static const MCPhysReg VecDbl[] = { in getCallerSavedRegs()
88 static const MCPhysReg VecPred[] = { in getCallerSavedRegs()
109 static const MCPhysReg Empty[] = { 0 }; in getCallerSavedRegs()
118 const MCPhysReg *
120 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
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