| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 30 namespace MCOI {
42 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
45 (1 << MCOI::EARLY_CLOBBER)
81 } // namespace MCOI
93 /// These are flags from the MCOI::OperandFlags enum.
105 return Flags & (1 << MCOI::LookupPtrRegClass); in isLookupPtrRegClass()
110 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } in isPredicate()
113 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef()
116 bool isBranchTarget() const { return Flags & (1 << MCOI
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCTargetDesc.cpp | 145 case MCOI::OPERAND_UNKNOWN: in evaluateBranch()
146 case MCOI::OPERAND_IMMEDIATE: { in evaluateBranch()
153 case MCOI::OPERAND_PCREL: in evaluateBranch()
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| H A D | MipsBaseInfo.h | 133 OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 71 OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
975 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
979 if (NumOps == 8 && Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias()
984 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
985 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
989 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
990 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias()
991 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) in getOperandBias()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.h | 439 SmallBitVector TypeIdxsCovered{MCOI::OPERAND_LAST_GENERIC -
440 MCOI::OPERAND_FIRST_GENERIC + 2};
441 SmallBitVector ImmIdxsCovered{MCOI::OPERAND_LAST_GENERIC_IMM -
442 MCOI::OPERAND_FIRST_GENERIC_IMM + 2};
447 (MCOI::OPERAND_LAST_GENERIC - MCOI::OPERAND_FIRST_GENERIC) && in typeIdx()
582 assert(ImmIdx <= (MCOI::OPERAND_LAST_GENERIC_IMM - in immIdx()
583 MCOI::OPERAND_FIRST_GENERIC_IMM) && in immIdx()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYBaseInfo.h | 63 OPERAND_BARESYMBOL = MCOI::OPERAND_FIRST_TARGET,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Disassembler/ |
| H A D | WebAssemblyDisassembler.cpp | 210 case MCOI::OPERAND_IMMEDIATE: { in getInstruction()
292 case MCOI::OPERAND_REGISTER: in getInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.h | 72 OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 234 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0; in isFirstDefTiedToFirstUse()
265 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCTargetDesc.cpp | 105 MCOI::OPERAND_PCREL) { in evaluateBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 114 OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
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| H A D | ARMMCTargetDesc.cpp | 422 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) { in evaluateBranch()
578 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY) in evaluateMemoryOperandAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 129 MCOI::OPERAND_PCREL) in evaluateBranch()
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| H A D | AMDGPUInstPrinter.cpp | 832 case MCOI::OPERAND_IMMEDIATE: in printRegularOperand()
873 case MCOI::OPERAND_UNKNOWN: in printRegularOperand()
874 case MCOI::OPERAND_PCREL: in printRegularOperand()
877 case MCOI::OPERAND_REGISTER: in printRegularOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1391 const MCOperandInfo &MCOI = MCID.operands()[I]; in foldMemoryOperandImpl() local
1392 if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum) in foldMemoryOperandImpl()
1394 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass); in foldMemoryOperandImpl()
2245 const MCOperandInfo &MCOI = MCID.operands()[I]; in verifyInstruction() local
2249 if (MCOI.OperandType == MCOI::OPERAND_MEMORY && in verifyInstruction()
2250 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) || in verifyInstruction()
2251 (MCOI.RegClass == -1 && !Op.isImm()))) { in verifyInstruction()
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| H A D | SystemZHazardRecognizer.cpp | 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
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| H A D | SystemZShortenInst.cpp | 69 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmTypeCheck.cpp | 415 if (Op.OperandType == MCOI::OPERAND_REGISTER) { in typeCheck()
424 assert(Op.OperandType == MCOI::OPERAND_REGISTER && "Register expected"); in typeCheck()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 2388 const MCOperandInfo &MCOI = MCID.operands()[MONum]; in visitMachineOperand() local
2391 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
2396 const MCOperandInfo &MCOI = MCID.operands()[MONum]; in visitMachineOperand() local
2402 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs()) in visitMachineOperand()
2409 if (MCOI.OperandType == MCOI::OPERAND_REGISTER && in visitMachineOperand()
2413 if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE || in visitMachineOperand()
2414 (MCOI.OperandType == MCOI::OPERAND_PCREL && in visitMachineOperand()
2420 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
2477 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVInstPrinter.cpp | 127 MCOI::OPERAND_UNKNOWN) { in printInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCTargetDesc.h | 51 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.cpp | 480 MCOI::OPERAND_PCREL) in evaluateBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 218 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads()
456 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVAsmPrinter.cpp | 980 assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 && in lowerRISCVVMachineInstrToMCInst()
985 if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) < in lowerRISCVVMachineInstrToMCInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIDefines.h | 200 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
|