| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 38 class MCInstrDesc; variable
374 const MCInstrDesc &MCID) { in BuildMI()
383 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
415 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
427 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
438 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
448 const MCInstrDesc &MCID) { in BuildMI()
460 const MCInstrDesc &MCID) { in BuildMI()
471 const MCInstrDesc &MCID) { in BuildMI()
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| H A D | DFAPacketizer.h | 45 class MCInstrDesc; variable
103 bool canReserveResources(const MCInstrDesc *MID);
107 void reserveResources(const MCInstrDesc *MID);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 25 class MCInstrDesc; variable
52 const MCInstrDesc &II,
67 const MCInstrDesc *II,
78 const MCInstrDesc *II,
111 const MCInstrDesc &DbgValDesc,
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| H A D | InstrEmitter.cpp | 130 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
188 const MCInstrDesc &II, in CreateVirtualRegisters()
320 const MCInstrDesc *II, in AddRegisterOperand()
329 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
401 const MCInstrDesc *II, in AddOperand()
662 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
756 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, in AddDbgValueLocationOps()
793 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF); in EmitDbgInstrRef()
925 const MCInstrDesc &Desc = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgNoLocation()
936 const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST); in EmitDbgValueList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
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| H A D | PPCExpandAtomicPseudoInsts.cpp | 55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
122 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicRMW128()
123 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicRMW128()
220 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicCmpSwap128()
221 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicCmpSwap128()
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| H A D | PPCFrameLowering.cpp | 660 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
662 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
664 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
666 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX in emitPrologue()
668 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
670 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 in emitPrologue()
672 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 in emitPrologue()
674 const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8 in emitPrologue()
676 const MCInstrDesc &StoreWordInst = TII.get(isPPC64 ? PPC::STW8 : PPC::STW); in emitPrologue()
677 const MCInstrDesc &HashST = in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 33 const MCInstrDesc *LastDesc; // Raw array to allow static init'n
48 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
63 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 20 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
32 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
40 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 646 ComponentProps(const MCInstrDesc &OpDesc);
789 ComponentInfo(const MCInstrDesc &OpDesc,
794 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps) in ComponentInfo()
810 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) in InstInfo()
854 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
1333 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1336 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1339 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1342 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1351 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 174 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) { in getVLOpNum()
185 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) { in getSEWOpNum()
194 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) { in getVecPolicyOpNum()
201 static inline int getFRMOpNum(const MCInstrDesc &Desc) { in getFRMOpNum()
216 static inline int getVXRMOpNum(const MCInstrDesc &Desc) { in getVXRMOpNum()
232 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) { in isFirstDefTiedToFirstUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86EncodingOptimization.h | 17 class MCInstrDesc; variable
19 bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 170 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isPredicated()
176 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isCPSRDefined()
186 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget()
417 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); in evaluateBranch()
440 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode_i12()
458 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode3()
478 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5()
497 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5FP16()
517 evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_i8s4()
538 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_pc()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 55 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
64 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
74 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
81 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 49 #include "llvm/MC/MCInstrDesc.h"
161 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
162 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
219 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
220 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
276 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
277 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
355 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
421 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
514 SmallVector<const MCInstrDesc*, MaxNumRep in optimizeLdStInterleave()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ReturnThunks.cpp | 82 const MCInstrDesc &CS = ST.getInstrInfo()->get(X86::CS_PREFIX); in runOnMachineFunction()
83 const MCInstrDesc &JMP = ST.getInstrInfo()->get(X86::TAILJMPd); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBuilder.h | 63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
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| H A D | M68kInstrInfo.h | 317 const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
320 bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
327 bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 432 const MCInstrDesc &DefMCID,
436 const MCInstrDesc &DefMCID,
440 const MCInstrDesc &UseMCID,
444 const MCInstrDesc &UseMCID,
448 const MCInstrDesc &DefMCID,
450 const MCInstrDesc &UseMCID,
456 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
458 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
919 const MCInstrDesc &Desc = TII->get(Opcode); in isLegalAddressImm()
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| H A D | MLxExpansionPass.cpp | 184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| H A D | ARMHazardRecognizer.cpp | 31 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
52 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
55 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.h | 24 class MCInstrDesc; variable
100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 131 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
198 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
378 const MCInstrDesc &MID = MI->getDesc(); in getBaseOpPosition()
400 const MCInstrDesc &MID = MI->getDesc(); in getOffsetOpPosition()
427 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
522 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
704 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
751 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/ |
| H A D | AMDGPUCustomBehaviour.cpp | 249 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
303 bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) { in isVMEM()
325 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 222 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc, in computeMaxLatency()
239 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) { in verifyOperands()
270 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateWrites()
445 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateReads()
567 const MCInstrDesc &MCDesc = MCII.get(Opcode); in createInstrDescImpl()
702 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in createInstruction()
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