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Searched refs:MCID (Results 1 – 25 of 84) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h144 namespace MCID {
256 bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); } in isPreISelOpcode()
262 bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); } in isVariadic()
266 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); } in hasOptionalDef()
270 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); } in isPseudo()
274 bool isMetaInstruction() const { return Flags & (1ULL << MCID::Meta); } in isMetaInstruction()
277 bool isReturn() const { return Flags & (1ULL << MCID::Return); } in isReturn()
280 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd()
283 bool isTrap() const { return Flags & (1ULL << MCID::Trap); } in isTrap()
286 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } in isMoveReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp250 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo() local
251 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
252 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
256 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
264 else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) in generateWaitCntInfo()
268 } else if (isVMEM(MCID) && !AMDGPU::getMUBUFIsBufferInv(Opcode)) { in generateWaitCntInfo()
271 else if ((MCID.mayLoad() && in generateWaitCntInfo()
272 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
273 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
274 !MCID.mayStore())) in generateWaitCntInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore() local
30 if (!MCID) in isLoadAfterStore()
33 if (!MCID->mayLoad()) in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet() local
56 if (!MCID) in isBCTRAfterSet()
59 if (!MCID->isBranch()) in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst() argument
90 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
123 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1) in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h374 const MCInstrDesc &MCID) { in BuildMI() argument
375 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL())) in BuildMI()
383 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
384 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL())) in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
398 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); in BuildMI()
415 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
417 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); in BuildMI()
427 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
431 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID, in BuildMI()
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H A DMachineInstr.h129 const MCInstrDesc *MCID; // Instruction descriptor.
582 const MCInstrDesc &getDesc() const { return *MCID; }
636 return getNumExplicitDefs() + MCID->implicit_defs().size();
907 return hasProperty(MCID::PreISelOpcode, Type);
915 return hasProperty(MCID::Variadic, Type);
921 return hasProperty(MCID::HasOptionalDef, Type);
927 return hasProperty(MCID::Pseudo, Type);
933 return hasProperty(MCID::Meta, Type);
937 return hasProperty(MCID::Return, Type);
943 return hasProperty(MCID::EHScopeReturn, Type);
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc(); variable
65 if (MCID.mayLoad())
67 if (MCID.mayStore())
80 const MCInstrDesc &MCID = MI->getDesc(); variable
82 if (MCID.mayLoad())
84 if (MCID.mayStore())
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp252 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef() argument
253 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
650 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
651 if (MCID.hasOptionalDef() && in ReduceSpecial()
652 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
813 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
814 if (MCID.hasOptionalDef()) { in ReduceTo2Addr()
815 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
837 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
839 if (i < NumOps && MCID.operands()[i].isOptionalDef()) in ReduceTo2Addr()
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H A DARMHazardRecognizer.cpp29 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
30 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
33 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
50 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
51 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
H A DMLxExpansionPass.cpp184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
185 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
188 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
346 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
356 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DValueMapper.cpp88 unsigned MCID : 29; member
164 unsigned MCID);
168 unsigned MCID);
170 unsigned MCID);
171 void scheduleRemapFunction(Function &F, unsigned MCID);
932 CurrentMCID = E.MCID; in flush()
1131 unsigned MCID) { in scheduleMapGlobalInitializer() argument
1133 assert(MCID < MCs.size() && "Invalid mapping context"); in scheduleMapGlobalInitializer()
1137 WE.MCID = MCID; in scheduleMapGlobalInitializer()
1147 unsigned MCID) { in scheduleMapAppendingVariable() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp122 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
123 if (!MCID) { in getHazardType()
127 unsigned idx = MCID->getSchedClass(); in getHazardType()
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
178 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction()
179 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction()
186 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
H A DMachineInstr.cpp91 for (MCPhysReg ImpDef : MCID->implicit_defs()) in addImplicitDefUseOperands()
93 for (MCPhysReg ImpUse : MCID->implicit_uses()) in addImplicitDefUseOperands()
102 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0), in MachineInstr()
107 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() + in MachineInstr()
108 MCID->implicit_uses().size()) { in MachineInstr()
121 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0), in MachineInstr()
148 MCID = &TID; in setDesc()
209 assert(MCID && "Cannot add operands before providing an instr descriptor"); in addOperand()
282 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand()
287 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) in addOperand()
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H A DBreakFalseDeps.cpp191 const MCInstrDesc &MCID = MI->getDesc(); in processDefs() local
195 for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { in processDefs()
217 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
H A DMachineVerifier.cpp1109 const MCInstrDesc &MCID = MI->getDesc(); in verifyPreISelGenericInstruction() local
1131 for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps); in verifyPreISelGenericInstruction()
1133 if (!MCID.operands()[I].isGenericType()) in verifyPreISelGenericInstruction()
1137 size_t TypeIdx = MCID.operands()[I].getGenericTypeIndex(); in verifyPreISelGenericInstruction()
1170 if (MI->getNumOperands() < MCID.getNumOperands()) in verifyPreISelGenericInstruction()
1437 assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}"); in verifyPreISelGenericInstruction()
2275 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
2276 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
2278 OS << MCID.getNumOperands() << " operands expected, but " in visitMachineInstrBefore()
2282 if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent()) in visitMachineInstrBefore()
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/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DCodeEmitter.cpp18 CodeEmitter::EncodingInfo CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) { in getOrCreateEncodingInfo() argument
19 EncodingInfo &EI = Encodings[MCID]; in getOrCreateEncodingInfo()
24 const MCInst &Inst = Sequence[MCID]; in getOrCreateEncodingInfo()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DCodeEmitter.h49 LLVM_ABI EncodingInfo getOrCreateEncodingInfo(unsigned MCID);
56 StringRef getEncoding(unsigned MCID) { in getEncoding() argument
57 EncodingInfo EI = getOrCreateEncodingInfo(MCID); in getEncoding()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h29 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local
31 if (MCID.mayLoad()) in addFrameReference()
33 if (MCID.mayStore()) in addFrameReference()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DLVLGen.cpp39 const MCInstrDesc &MCID = TII->get(Opcode); in getVLIndex() local
42 if (HAS_VLINDEX(MCID.TSFlags)) in getVLIndex()
43 return GET_VLINDEX(MCID.TSFlags); in getVLIndex()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp244 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
245 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
246 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
251 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
417 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
418 assert(!MCID.implicit_defs().empty() && in getPhysicalRegisterVT()
420 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
421 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT()
517 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
518 for (MCPhysReg Reg : MCID.implicit_defs()) in DelayForLiveRegsBottomUp()
H A DScheduleDAGSDNodes.cpp216 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in ClusterNeighboringLoads() local
217 for (unsigned I = 0; I != MCID.getNumOperands(); ++I) { in ClusterNeighboringLoads()
218 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads()
322 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
323 if (MCID.mayLoad()) in ClusterNodes()
454 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
455 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in AddSchedEdges()
456 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
461 if (MCID.isCommutable()) in AddSchedEdges()
H A DScheduleDAGRRList.cpp1031 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in TryUnfoldSU() local
1032 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in TryUnfoldSU()
1033 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU()
1038 if (MCID.isCommutable()) in TryUnfoldSU()
1280 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1281 assert(!MCID.implicit_defs().empty() && in getPhysicalRegisterVT()
1283 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1284 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT()
1422 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
1423 if (MCID.hasOptionalDef()) { in DelayForLiveRegsBottomUp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init() local
98 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
101 for (MCPhysReg ImpUse : MCID.implicit_uses()) in init()
109 for (MCPhysReg R : MCID.implicit_defs()) { in init()
110 if (Hexagon::R31 != R && MCID.isCall()) in init()
135 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
188 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp630 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
633 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); in convert()
635 BuildMI(*Head, Head->end(), TermDL, MCID) in convert()
642 TII->getRegClass(MCID, 1, TRI, *MF)); in convert()
687 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
689 TII->getRegClass(MCID, 0, TRI, *MF)); in convert()
692 TII->getRegClass(MCID, 1, TRI, *MF)); in convert()
693 MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID) in convert()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerInfo.cpp406 const MCInstrDesc &MCID = MII.get(Opcode); in verify() local
408 MCID.operands().begin(), MCID.operands().end(), 0U, in verify()
415 MCID.operands().begin(), MCID.operands().end(), 0U, in verify()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h199 const MCInstrDesc &MCID = MI->getDesc(); variable
201 if (MCID.mayLoad())
203 if (MCID.mayStore())

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