| /freebsd/contrib/ofed/opensm/include/vendor/ |
| H A D | osm_vendor.h | 69 #error No MAD Interface selected!
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| /freebsd/share/monetdef_unicode/ |
| H A D | ar_MA.UTF-8.src | 7 MAD
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrHFP.td | 195 def MAD : TernaryRXF<"mad", 0xED3E, null_frag, FP64, FP64, z_load, 8>;
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| /freebsd/usr.bin/units/ |
| H A D | definitions.units | 453 MAD moroccodirham
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 7517 MachineInstr *MAD = MRI.getUniqueVRegDef(Root.getOperand(1).getReg()); in genFNegatedMAD() local
7520 const TargetRegisterClass *RC = MRI.getRegClass(MAD->getOperand(0).getReg()); in genFNegatedMAD()
7529 Register SrcReg0 = MAD->getOperand(1).getReg(); in genFNegatedMAD()
7530 Register SrcReg1 = MAD->getOperand(2).getReg(); in genFNegatedMAD()
7531 Register SrcReg2 = MAD->getOperand(3).getReg(); in genFNegatedMAD()
7532 bool Src0IsKill = MAD->getOperand(1).isKill(); in genFNegatedMAD()
7533 bool Src1IsKill = MAD->getOperand(2).isKill(); in genFNegatedMAD()
7534 bool Src2IsKill = MAD->getOperand(3).isKill(); in genFNegatedMAD()
7551 return MAD; in genFNegatedMAD()
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| H A D | AArch64SchedNeoverseV1.td | 1623 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;
1627 def : InstRW<[V1Write_4c_1V0], (instregex "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
1746 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;
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| H A D | AArch64SchedA510.td | 898 "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;
902 "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;
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| H A D | AArch64SchedA320.td | 920 "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;
924 "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;
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| H A D | AArch64SchedNeoverseV2.td | 2352 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;
2358 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;
2548 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;
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| H A D | AArch64SchedNeoverseN2.td | 1861 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
1865 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;
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| H A D | AArch64SchedNeoverseN3.td | 1831 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
1835 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;
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| H A D | AArch64TargetTransformInfo.cpp | 2252 if (auto MAD = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul, in instCombineSVEVectorAdd() local
2255 return MAD; in instCombineSVEVectorAdd()
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| H A D | AArch64SchedA64FX.td | 2086 (instregex "^FABD_Z", "^F(ADD|SUBR?)_.*Z_", "^FN?(MAD|MLA|MLS|MSB)_ZP",
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| H A D | SVEInstrFormats.td | 3589 //class for generating pseudo for SVE MLA/MAD/MLS/MSB
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | CodeGenOptions.def | 157 CODEGENOPT(LessPreciseFPMAD , 1, 0, Benign) ///< Enable less precise MAD instructions to
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 963 multiclass MAD<string Ptx, ValueType VT, NVPTXRegClass Reg, Operand Imm> {
988 defm MAD16 : MAD<"mad.lo.s16", i16, B16, i16imm>;
989 defm MAD32 : MAD<"mad.lo.s32", i32, B32, i32imm>;
990 defm MAD64 : MAD<"mad.lo.s64", i64, B64, i64imm>;
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| H A D | NVPTXISelLowering.cpp | 4871 SDValue MAD = DCI.DAG.getNode(ISD::ADD, DL, VT, Mul, N1); in PerformADDCombineWithOperands() local
4873 ((ZeroOpNum == 1) ? N1 : MAD), in PerformADDCombineWithOperands()
4874 ((ZeroOpNum == 1) ? MAD : N1)); in PerformADDCombineWithOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | VOP3PInstructions.td | 153 // that FMA and MAD will differ.
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| /freebsd/contrib/llvm-project/clang/include/clang/Driver/ |
| H A D | Options.td | 1084 HelpText<"OpenCL only. Allow use of less precise MAD computations in the generated binary.">,
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| /freebsd/crypto/heimdal/lib/wind/ |
| H A D | NormalizationTest.txt | 5856 B9CF;B9CF;1106 1161 11AE;B9CF;1106 1161 11AE; # (맏; 맏; 맏; 맏; 맏; ) HANGUL SYLLABLE MAD
|